Alternatives and similar repositories for lefdef-toolkit:

Users that are interested in lefdef-toolkit are comparing it to the libraries listed below

• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆27Updated 5 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 4 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 2 years ago
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆14Updated 6 years ago
• cibyr / lefdef
  Library Exchange Format (LEF) and Design Exchange Format (DEF)
  ☆18Updated 4 years ago
• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆20Updated 6 years ago
• ruykaji / lefdef-python
  Python iterface for Cadence LEF/DEF parser.
  ☆15Updated last year
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆38Updated 5 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆27Updated 2 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆53Updated 4 years ago
• Ravenslofty / librecell
  ☆20Updated 3 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆49Updated 4 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆82Updated 4 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆27Updated last year
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆30Updated 5 years ago
• ABKGroup / RosettaStone
  ☆23Updated 2 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆71Updated 7 years ago
• parallaxsw / OpenSTA
  ☆55Updated this week
• eclufsc / libertyParser
  Mirror of Synopsys's Liberty parser library
  ☆19Updated 6 years ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆54Updated 2 years ago
• lrakai / gate-sizing
  Optimal gate sizing of digital circuits using geometric programming
  ☆10Updated 8 years ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆122Updated 6 months ago
• ABKGroup / PROBE3.0
  ☆37Updated 9 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆41Updated 2 weeks ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆17Updated last year
• ABKGroup / TritonRoute-WXL
  ☆26Updated 4 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆126Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆37Updated 2 months ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆28Updated 9 years ago