Source code for LEF/DEF
☆11Oct 16, 2018Updated 7 years ago
Alternatives and similar repositories for lefdef-toolkit
Users that are interested in lefdef-toolkit are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A LEF/DEF Utility.☆34Aug 15, 2019Updated 6 years ago
- Library Exchange Format (LEF) and Design Exchange Format (DEF)☆27Aug 13, 2020Updated 5 years ago
- Parser and Viewer for Cadence® Library Exchange Format (LEF) and Design Exchange Format (DEF) integrated circuit (IC) description languag…☆17May 31, 2023Updated 3 years ago
- ☆21Jan 7, 2026Updated 7 months ago
- ☆25May 8, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Machine Learning Xgboost☆16Mar 31, 2020Updated 6 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆136Apr 23, 2023Updated 3 years ago
- Problem B: 3D Placement with D2D Vertical Connections☆11Jun 30, 2022Updated 4 years ago
- A GUI to help users visualize the structure of a verilog HDL project☆12Jul 26, 2015Updated 11 years ago
- Demonstration of using Caffe2 inside an Android application.☆10Dec 23, 2018Updated 7 years ago
- Python iterface for Cadence LEF/DEF parser.☆38Oct 31, 2023Updated 2 years ago
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 13 years ago
- Implementation of several grid routers in Rust☆13Jun 16, 2026Updated last month
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- General purpose task runner☆12Nov 10, 2025Updated 9 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆153Feb 27, 2023Updated 3 years ago
- A Standalone Structural Verilog Parser☆97Mar 31, 2022Updated 4 years ago
- Log file scanner used with EDA tools to classify errors and warnings☆13Nov 14, 2022Updated 3 years ago
- Taiwei-3D-Flow☆59Jul 30, 2026Updated last week
- ☆21Sep 15, 2024Updated last year
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 8 months ago
- 基于vditor实现的vue版本的markdown编辑器☆13Jul 1, 2021Updated 5 years ago
- This library contains rectilinear spanning graph construction, finding minimum spanning tree and an implementation of binary search tree☆10Aug 22, 2015Updated 10 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆20Jan 4, 2024Updated 2 years ago
- core placement optimization☆13Dec 25, 2021Updated 4 years ago
- This project is to list the best books, courses, tutorial, methods on learning certain knowledge☆11Mar 22, 2021Updated 5 years ago
- discrete gate sizing☆14Nov 23, 2020Updated 5 years ago
- Database and Tool Framework for EDA☆127Jan 25, 2021Updated 5 years ago
- Python-based Verilog Parser (currently Netlist only)☆54Apr 12, 2017Updated 9 years ago
- Word-level sequence to sequence RNN for translation☆10Apr 7, 2017Updated 9 years ago
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- ☆125Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆11Apr 25, 2020Updated 6 years ago
- Implement of "RAISR: Rapid and Accurate Image Super Resolution"☆30Feb 28, 2018Updated 8 years ago
- thread-safe python object pool☆13Mar 22, 2019Updated 7 years ago
- 🚀 LLM inference optimization simulator, modeling compute-bound prefill and memory-bound decode phases.☆13Jul 12, 2025Updated last year
- symmetric clock tree synthesis for NTV IC design☆11May 8, 2022Updated 4 years ago
- Converts GDSII (IC layout database) files to SVG (Vector graphics) files.☆17Feb 10, 2023Updated 3 years ago
- ☆16Jun 30, 2024Updated 2 years ago