brandonhamilton / GPGPULinks
General Purpose Graphics Processing Unit (GPGPU) IP Core
☆11Updated 11 years ago
Alternatives and similar repositories for GPGPU
Users that are interested in GPGPU are comparing it to the libraries listed below
Sorting:
- For CPU experiment☆12Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 10 months ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- The official NaplesPU hardware code repository☆17Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 9 months ago
- ☆71Updated last week
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- ☆27Updated 5 years ago
- matrix-coprocessor for RISC-V☆19Updated 3 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆19Updated 2 months ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 5 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- ☆10Updated 3 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated 2 weeks ago
- ☆29Updated 5 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆35Updated last year
- ☆30Updated 2 weeks ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆32Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆20Updated 11 months ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- cycle accurate Network-on-Chip Simulator☆28Updated 2 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- ☆52Updated 6 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆14Updated 4 months ago
- ☆13Updated 2 years ago
- APB UVC ported to Verilator☆11Updated last year