brandonhamilton / GPGPU
General Purpose Graphics Processing Unit (GPGPU) IP Core
☆11Updated 10 years ago
Alternatives and similar repositories for GPGPU:
Users that are interested in GPGPU are comparing it to the libraries listed below
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated last week
- ☆24Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 3 months ago
- ☆41Updated 6 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆23Updated this week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- APB UVC ported to Verilator☆11Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 4 months ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- A Verilog implementation of a processor cache.☆24Updated 7 years ago
- ☆25Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆28Updated 4 months ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆15Updated last week
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆17Updated 6 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated last month
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last week
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- ☆23Updated last month
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- Simple single-port AXI memory interface☆37Updated 8 months ago
- Original test vector of RISC-V Vector Extension☆11Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago