OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
☆23Aug 6, 2026Updated this week
Alternatives and similar repositories for obi
Users that are interested in obi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆16May 6, 2026Updated 3 months ago
- RISC-V Worlds provides isolation in a hardware platform by constraining access to system physical addresses.☆15Aug 4, 2026Updated last week
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v☆13Dec 6, 2021Updated 4 years ago
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…☆25Jul 1, 2026Updated last month
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 3 years ago
- APB Logic☆29Updated this week
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- DNN Compiler for Heterogeneous SoCs☆73Aug 4, 2026Updated last week
- SystemVerilog IPs and Modules for architectural redundancy designs.☆21Updated this week
- A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012)☆12Jan 8, 2021Updated 5 years ago
- ☆15Jun 26, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Jul 16, 2026Updated 3 weeks ago
- RISC-V Integration for PYNQ☆12Apr 10, 2020Updated 6 years ago
- A Fast, Low-Overhead On-chip Network☆326Updated this week
- USB2.0 Device Controller IP Core☆18Aug 18, 2023Updated 2 years ago
- A reliable, real-time subsystem for the Carfield SoC☆21Dec 2, 2025Updated 8 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆67Jul 17, 2026Updated 3 weeks ago
- A Vivado IP package of the PicoRV32 RISC-V processor☆15Jul 9, 2020Updated 6 years ago
- 4th RISC-V Workshop Tutorials☆13Jul 19, 2016Updated 10 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- spike-vp☆13Feb 5, 2024Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆226Updated this week
- ☆26Jul 22, 2026Updated 2 weeks ago
- Hardware Design/Visualization/Simulation/RTLGeneration Framework☆18Jul 30, 2026Updated last week
- Modular, flexible, cross-platform workload profiling and characterization☆13Mar 1, 2021Updated 5 years ago
- ☆15Jan 14, 2025Updated last year
- Reticle evaluation (PLDI 2021)☆12Apr 12, 2021Updated 5 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆264Updated this week
- high abstraction synthesis☆13Apr 8, 2024Updated 2 years ago
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆17Mar 3, 2018Updated 8 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆29Jul 7, 2026Updated last month
- ☆10Feb 13, 2025Updated last year
- AXI4 with a FIFO integrated with VIP☆25Feb 29, 2024Updated 2 years ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆19Jul 25, 2023Updated 3 years ago