psnjk / SimpleCacheLinks
Simple cache design implementation in verilog
☆50Updated last year
Alternatives and similar repositories for SimpleCache
Users that are interested in SimpleCache are comparing it to the libraries listed below
Sorting:
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆40Updated 3 years ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆45Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- ☆36Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- ☆64Updated 3 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆66Updated last year
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆78Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆80Updated last year
- AXI Interconnect☆53Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated last month
- round robin arbiter☆75Updated 11 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆85Updated last year
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆64Updated 4 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆53Updated last year
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆55Updated 5 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 10 months ago
- A Verilog implementation of a processor cache.☆28Updated 7 years ago
- This is the repository for the IEEE version of the book☆73Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago
- Introductory course into static timing analysis (STA).☆97Updated 3 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- ☆48Updated 4 years ago