Simple cache design implementation in verilog
☆55Nov 20, 2023Updated 2 years ago
Alternatives and similar repositories for SimpleCache
Users that are interested in SimpleCache are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Verilog implementation of a processor cache.☆39Dec 29, 2017Updated 8 years ago
- Various caches written in Verilog-HDL☆131Apr 24, 2015Updated 11 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆47Jun 13, 2023Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆14Nov 4, 2022Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- LZW Compressoion algorithm in verilog☆17Dec 19, 2013Updated 12 years ago
- Two Level Cache Controller implementation in Verilog HDL☆62Jul 9, 2020Updated 5 years ago
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 14 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- Kogge-Stone Adder in Verilog☆16Nov 19, 2021Updated 4 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 7 years ago
- Verilog implementation of various types of CPUs☆79Sep 27, 2019Updated 6 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆21Dec 8, 2012Updated 13 years ago
- Implementation of Direct-Mapped-Cache to hold 256 blocks, 16 32-bit instruction/Data per block with 32-bit address line☆15Dec 29, 2018Updated 7 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆42Oct 23, 2016Updated 9 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆27Jun 4, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog Configurable Cache☆198Updated this week
- Simple sram controller in verilog.☆36Jun 5, 2016Updated 9 years ago
- Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog☆20Mar 11, 2021Updated 5 years ago
- AES-based-on-FPGA developed by verilog.☆23Apr 23, 2020Updated 6 years ago
- Implementation of Sobel Filter in Verilog☆27Mar 10, 2017Updated 9 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆141May 14, 2021Updated 5 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated last year
- Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algor…☆26May 5, 2015Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆16Nov 9, 2023Updated 2 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆31Oct 9, 2020Updated 5 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Apr 15, 2021Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆163Nov 2, 2020Updated 5 years ago
- I2S transciever implemented in Verilog HDL☆33Oct 11, 2017Updated 8 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆19Oct 18, 2023Updated 2 years ago