seifhelal / Cache-SimulatorLinks
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
☆22Updated 8 years ago
Alternatives and similar repositories for Cache-Simulator
Users that are interested in Cache-Simulator are comparing it to the libraries listed below
Sorting:
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆144Updated 3 years ago
- Verilog/SystemVerilog Guide☆78Updated 2 years ago
- An overview of TL-Verilog resources and projects☆82Updated 3 weeks ago
- ☆63Updated 4 years ago
- SystemC training aimed at TLM.☆34Updated 5 years ago
- Ariane is a 6-stage RISC-V CPU☆151Updated 6 years ago
- Advanced Architecture Labs with CVA6☆72Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆141Updated 7 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆117Updated 5 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆144Updated 6 years ago
- Vector processor for RISC-V vector ISA☆133Updated 5 years ago
- Championship Branch Prediction 2025☆67Updated 7 months ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆57Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆194Updated last week
- Topics in Machine Learning Accelerator Design☆91Updated 2 years ago
- This repository contains the design files of RISC-V Pipeline Core☆61Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆130Updated 3 months ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆17Updated 9 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆56Updated 5 years ago
- Network on Chip Simulator☆299Updated 2 months ago
- A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall☆57Updated 11 months ago
- A Fast, Low-Overhead On-chip Network☆257Updated 3 weeks ago
- This is a verilog implementation of 4x4 systolic array multiplier☆71Updated 5 years ago
- Implementation of a cache memory in verilog☆15Updated 8 years ago
- NoC simulation using gem5 (a simple tul)☆13Updated last year
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆39Updated last year
- A verilog implementation for Network-on-Chip☆79Updated 7 years ago