Alternatives and similar repositories for Cache-Simulator:

Users that are interested in Cache-Simulator are comparing it to the libraries listed below

• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆27Updated 4 years ago
• anishagartia / Cache-Coherence
  Implementation of MI, MSI, MESI, MOSI, MOESI, MOESIF protocols in Cache Coherence
  ☆15Updated 8 years ago
• matbi86 / 01_ai_accelerator_basic_for_student
  ai_accelerator_basic_for_student (no solve)
  ☆11Updated 4 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆39Updated 4 years ago
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆69Updated 5 years ago
• Chun-Feng / CACTI-6.5
  This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…
  ☆14Updated 8 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆62Updated 2 weeks ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆41Updated 3 years ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆59Updated last year
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆62Updated last week
• gem5bootcamp / gem5-bootcamp-env
  The gem5 Bootcamp 2022 environment. Archived.
  ☆36Updated 6 months ago
• tom01h / zero-riscy
  zero-riscy CPU Core
  ☆15Updated 6 years ago
• 0xd3ba / build-your-own-prefetcher
  This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator
  ☆35Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆60Updated last year
• digital-design-hq / Digital-Resources
  ☆54Updated 3 years ago
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆128Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆32Updated 3 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆49Updated 3 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆54Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• srikantaggarwal / Cache-Coherence
  Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a b…
  ☆11Updated 10 years ago
• shrut1996 / Cache-Implementation
  Implementation of a cache memory in verilog
  ☆13Updated 7 years ago
• prasadp4009 / 2-way-Set-Associative-Cache-Controller
  Synthesizable and Parameterized Cache Controller in Verilog
  ☆41Updated last year
• jieltan / OpenCompArchCourse
  ☆20Updated 3 years ago
• ic-lab-duth / DRIM
  DUTH RISC-V Microprocessor
  ☆19Updated last month
• black-parrot / black-parrot-sim
  ☆12Updated last month
• andreaskuster / black-parrot-branch-predictor
  Branch Predictor Optimization for BlackParrot
  ☆14Updated 9 months ago
• akilm / FPU-IEEE-754
  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…
  ☆47Updated 5 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆72Updated 3 weeks ago