Alternatives and similar repositories for Cache-Simulator:

Users that are interested in Cache-Simulator are comparing it to the libraries listed below

• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆65Updated last year
• anishagartia / Cache-Coherence
  Implementation of MI, MSI, MESI, MOSI, MOESI, MOESIF protocols in Cache Coherence
  ☆16Updated 8 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆58Updated last year
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆34Updated 10 months ago
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆72Updated 6 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆28Updated 3 years ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆28Updated 4 years ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆14Updated 2 years ago
• zli87 / Wishbone-to-I2C-bus-controller-IP-Verification
  ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.
  ☆18Updated 2 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆42Updated 4 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆51Updated 3 years ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆24Updated 3 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆27Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆71Updated last week
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• akilm / FPU-IEEE-754
  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…
  ☆51Updated 8 months ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆50Updated 4 years ago
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆38Updated 6 years ago
• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆124Updated this week
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆75Updated 3 years ago
• srikantaggarwal / Cache-Coherence
  Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a b…
  ☆11Updated 10 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆74Updated 10 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆65Updated 5 years ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆64Updated last year
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆24Updated last year
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆117Updated 4 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago