seifhelal / Cache-Simulator
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
☆19Updated 7 years ago
Alternatives and similar repositories for Cache-Simulator:
Users that are interested in Cache-Simulator are comparing it to the libraries listed below
- This is a verilog implementation of 4x4 systolic array multiplier☆48Updated 4 years ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆15Updated 8 years ago
- SystemC training aimed at TLM.☆27Updated 4 years ago
- gem5 repository to study chiplet-based systems☆68Updated 5 years ago
- Materials, slides, and workspace for the gem5 bootcamp 2024☆25Updated 6 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆67Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆120Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Implementation of MI, MSI, MESI, MOSI, MOESI, MOESIF protocols in Cache Coherence☆15Updated 8 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆125Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- Modeling Architectural Platform☆178Updated this week
- Topics in Machine Learning Accelerator Design☆67Updated 2 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated last year
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆129Updated 2 years ago
- Fast and accurate DRAM power and energy estimation tool☆147Updated last week
- A simple processor implemented in SystemC☆24Updated 8 years ago
- Vector processor for RISC-V vector ISA☆114Updated 4 years ago
- ☆54Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago
- The official repository for the gem5 resources sources.☆63Updated 2 weeks ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆178Updated 4 years ago
- A Chisel RTL generator for network-on-chip interconnects☆183Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆18Updated 10 months ago
- Unit tests generator for RVV 1.0☆77Updated last month
- ☆74Updated this week
- HLS for Networks-on-Chip☆33Updated 4 years ago
- ☆56Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆38Updated 8 months ago