seifhelal / Cache-SimulatorLinks
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
☆22Updated 8 years ago
Alternatives and similar repositories for Cache-Simulator
Users that are interested in Cache-Simulator are comparing it to the libraries listed below
Sorting:
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆412Updated last year
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆189Updated 3 weeks ago
- Network on Chip Simulator☆287Updated 2 months ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆138Updated 3 years ago
- It contains a curated list of awesome RISC-V Resources.☆259Updated 8 months ago
- SystemC training aimed at TLM.☆32Updated 5 years ago
- Modeling Architectural Platform☆208Updated last week
- Topics in Machine Learning Accelerator Design☆87Updated 2 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆306Updated 2 weeks ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆210Updated 4 months ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆198Updated 5 years ago
- Ariane is a 6-stage RISC-V CPU☆146Updated 5 years ago
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆402Updated 2 months ago
- Vector processor for RISC-V vector ISA☆128Updated 4 years ago
- Advanced Architecture Labs with CVA6☆68Updated last year
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆658Updated 2 years ago
- BookSim 2.0☆369Updated last year
- An overview of TL-Verilog resources and projects☆82Updated 6 months ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆307Updated 7 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆63Updated last year
- Verilog/SystemVerilog Guide☆73Updated last year
- This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator☆41Updated 3 years ago
- The Sniper Multi-Core Simulator☆149Updated 11 months ago
- Championship Branch Prediction 2025☆59Updated 4 months ago
- A Fast, Low-Overhead On-chip Network☆228Updated this week
- ☆28Updated 8 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆136Updated 5 years ago
- A Chisel RTL generator for network-on-chip interconnects☆211Updated last month
- gem5 repository to study chiplet-based systems☆81Updated 6 years ago