Sidshx / LLC-cache-simulatorLinks
A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement, multi-mode simulations, and comprehensive testing strategies for optimized processor performance.
☆15Updated 2 months ago
Alternatives and similar repositories for LLC-cache-simulator
Users that are interested in LLC-cache-simulator are comparing it to the libraries listed below
Sorting:
- ☆82Updated 11 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Updated 3 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- SystemVerilog modules and classes commonly used for verification☆57Updated last month
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- A collection of commonly asked RTL design interview questions☆38Updated 8 years ago
- ☆40Updated 2 weeks ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- ☆29Updated last year
- Implementation of the PCIe physical layer☆60Updated 7 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆100Updated 2 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆144Updated 7 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- Implementing Different Adder Structures in Verilog☆74Updated 6 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆56Updated 4 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆40Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆45Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆74Updated last year
- Verilog RTL Design☆46Updated 4 years ago
- round robin arbiter☆77Updated 11 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆71Updated last year
- ☆70Updated 3 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆24Updated 11 months ago
- Simple cache design implementation in verilog☆54Updated 2 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- A 2D convolution hardware implementation written in Verilog☆51Updated 5 years ago