Sidshx / LLC-cache-simulatorLinks
A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement, multi-mode simulations, and comprehensive testing strategies for optimized processor performance.
☆10Updated 6 months ago
Alternatives and similar repositories for LLC-cache-simulator
Users that are interested in LLC-cache-simulator are comparing it to the libraries listed below
Sorting:
- ☆22Updated 3 months ago
- Secbench is an open-source framework for hardware security characterization☆18Updated 3 weeks ago
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆11Updated 3 weeks ago
- OpenVAF revived by community☆11Updated 4 months ago
- A RISC-V RV32 model ready for SMT program synthesis.☆11Updated 4 years ago
- Running Linux on IOb-SoC-OpenCryptoHW☆14Updated 11 months ago
- Submission template for Tiny Tapeout 10 - Verilog HDL Projects☆24Updated 2 weeks ago
- Developing Smith Waterman accelerators on F1 instances using 1st CLaaS☆12Updated 2 years ago
- A project implementing Flappy Bird using Verilog☆8Updated 6 months ago
- ☆11Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. Work in Progress.☆13Updated 8 months ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆14Updated 9 months ago
- Source files to reproduce the results shown for A-QED at DAC 2020☆8Updated 4 years ago
- All Digital Phase-Locked Loop (ADPLL)☆13Updated last year
- NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…☆17Updated 4 years ago
- ☆14Updated last month
- BreakHammer is a technique that reduces the performance overhead of RowHammer mitigation mechanisms by carefully reducing the number of p…☆7Updated 7 months ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆12Updated last year
- Demo: how to create a custom EBRICK☆21Updated 7 months ago
- biRISC-V - 32-bit dual issue RISC-V CPU Software Environment☆13Updated 4 years ago
- Wraps the NVDLA project for Chipyard integration☆21Updated 3 months ago
- ☆19Updated last month
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆13Updated 3 weeks ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 3 years ago
- Creating energy-efficient inference solutions through the DiffLogic architecture, leveraging FPGAs to reduce data center power consumptio…☆10Updated 3 months ago
- Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆13Updated 6 months ago
- Tiny Tapeout GDS Action (using OpenLane)☆12Updated 2 weeks ago
- a Python framework for managing embedded HW/SW projects☆17Updated this week
- CMake based hardware build system☆29Updated 2 weeks ago
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆9Updated last month