max2468tw / IC_LabLinks
NCTU 2018 Spring Integrated Circuit Design Laboratory
☆24Updated 7 years ago
Alternatives and similar repositories for IC_Lab
Users that are interested in IC_Lab are comparing it to the libraries listed below
Sorting:
- ☆13Updated 4 years ago
- ☆36Updated 2 years ago
- IC Contest☆37Updated 2 years ago
- 交通大學iclab 2023 fall☆31Updated 9 months ago
- [NYCU 2021 Spring] Digital Circuits and Systems☆18Updated last year
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Updated 8 years ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南,含資源整理☆87Updated 3 months ago
- Computer-Aided VLSI System Design☆20Updated 8 months ago
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆123Updated 10 months ago
- ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.☆18Updated 2 years ago
- 紀錄一下自己寫過的所有Lab☆32Updated last year
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆183Updated 2 years ago
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆13Updated 2 years ago
- ☆18Updated 2 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆38Updated last year
- ☆12Updated 3 years ago
- ☆18Updated 3 months ago
- IC-contest 2012~2024☆18Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆63Updated last year
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆14Updated 5 years ago
- ☆26Updated 7 months ago
- Two Level Cache Controller implementation in Verilog HDL☆49Updated 5 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- ☆37Updated 2 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆22Updated last year
- ☆34Updated 6 years ago
- ☆33Updated 10 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago