NCTU 2018 Spring Integrated Circuit Design Laboratory
☆25Jun 25, 2018Updated 7 years ago
Alternatives and similar repositories for IC_Lab
Users that are interested in IC_Lab are comparing it to the libraries listed below
Sorting:
- Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.☆24Sep 21, 2021Updated 4 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆200Apr 2, 2023Updated 2 years ago
- ☆43Apr 6, 2023Updated 2 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- C++ implementation for Sequence Pair fixed-outline chip floorplanner☆11Dec 27, 2022Updated 3 years ago
- A simulator integrates ChampSim and Ramulator.☆19Aug 18, 2025Updated 7 months ago
- 交通大學iclab 2023 fall☆46Oct 18, 2024Updated last year
- ☆33Jan 6, 2026Updated 2 months ago
- 紀錄一下自己寫過的所有Lab☆37Jan 18, 2024Updated 2 years ago
- ☆11Mar 19, 2025Updated last year
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆158Sep 9, 2024Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆60Jul 9, 2020Updated 5 years ago
- Simple UART implementation in VHDL☆12Sep 10, 2015Updated 10 years ago
- Hardware Description Language on FPGA☆10Sep 18, 2023Updated 2 years ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理☆120Apr 9, 2025Updated 11 months ago
- Synthesizable and Parameterized Cache Controller in Verilog☆45Jun 13, 2023Updated 2 years ago
- ICCAD-2021-B☆12Aug 5, 2021Updated 4 years ago
- This project is made to generate Polar decoders (unrolled decoders).☆15May 31, 2025Updated 9 months ago
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆14Mar 3, 2023Updated 3 years ago
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- A Verilog implementation of a processor cache.☆37Dec 29, 2017Updated 8 years ago
- 交大電子所-積體電路實驗設計-李鎮宜教授☆14Sep 4, 2024Updated last year
- FPGA Games Gathered from GitHub in one place☆23Aug 19, 2022Updated 3 years ago
- This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…☆14Jun 7, 2025Updated 9 months ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Data Structure and Algorithm with C (2021 Spring)☆11Jan 22, 2026Updated last month
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast See…☆11Feb 5, 2018Updated 8 years ago
- A simplified cache simulator for instructional purposes☆15Dec 30, 2020Updated 5 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆14Aug 23, 2024Updated last year
- Implementing the Precise Runahead (HPCA'20) in gem5☆14Oct 5, 2023Updated 2 years ago
- Computer-aided VLSI System design, EEE 5022, National Taiwan University, 2018 Spring☆19Sep 19, 2018Updated 7 years ago
- ☆12Apr 16, 2022Updated 3 years ago
- ☆17May 9, 2022Updated 3 years ago
- Integrated Circuit Design Contest (ICDC) - 大學院校積體電路設計競賽☆23Apr 20, 2022Updated 3 years ago
- Verilog implementation of Bresenham's line drawing algorithm.☆13Nov 22, 2015Updated 10 years ago
- Polar codes are error correction codes developed by Erdal Arikan which achieves channel capacity and its reduced complexity makes it more…☆19Jul 22, 2021Updated 4 years ago
- Not All Patches Are Equal: Hierarchical Dataset Condensation for Single Image Super-Resolution☆10May 7, 2024Updated last year