NCTU 2018 Spring Integrated Circuit Design Laboratory
☆26Jun 25, 2018Updated 8 years ago
Alternatives and similar repositories for IC_Lab
Users that are interested in IC_Lab are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.☆24Sep 21, 2021Updated 4 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆209Apr 2, 2023Updated 3 years ago
- ☆44Apr 6, 2023Updated 3 years ago
- ☆12Aug 26, 2016Updated 10 years ago
- C++ implementation for Sequence Pair fixed-outline chip floorplanner☆12Dec 27, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A simulator integrates ChampSim and Ramulator.☆23Updated this week
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆177Sep 9, 2024Updated last year
- 交通大學iclab 2023 fall☆53Oct 18, 2024Updated last year
- 紀錄一下自己寫過的所有Lab☆40Jan 18, 2024Updated 2 years ago
- ☆14Mar 19, 2025Updated last year
- ☆39Jun 13, 2026Updated 2 months ago
- Two Level Cache Controller implementation in Verilog HDL☆66Jul 9, 2020Updated 6 years ago
- Simple UART implementation in VHDL☆11Sep 10, 2015Updated 10 years ago
- ICCAD-2021-B☆12Aug 5, 2021Updated 5 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Professor: C.H. Yang☆10Aug 16, 2025Updated last year
- Synthesizable and Parameterized Cache Controller in Verilog☆49Jun 13, 2023Updated 3 years ago
- C++ implementation for Fiduccia-Mattheyses Heuristic☆11Jan 9, 2023Updated 3 years ago
- Hardware Description Language on FPGA☆11Sep 18, 2023Updated 2 years ago
- This project is made to generate Polar decoders (unrolled decoders).☆15May 31, 2025Updated last year
- FPGA Games Gathered from GitHub in one place☆22Aug 19, 2022Updated 4 years ago
- Data Structure and Algorithm with C (2021 Spring)☆11Jul 20, 2026Updated last month
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆14Mar 3, 2023Updated 3 years ago
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 交大電子所-積體電路實驗設計-李鎮宜教授☆14Sep 4, 2024Updated last year
- ☆13Feb 13, 2022Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 5 years ago
- A Verilog implementation of a processor cache.☆40Dec 29, 2017Updated 8 years ago
- This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…☆14Jun 7, 2025Updated last year
- Computer-aided VLSI System design, EEE 5022, National Taiwan University, 2018 Spring☆19Sep 19, 2018Updated 7 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- A simplified cache simulator for instructional purposes☆15Dec 30, 2020Updated 5 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Implementing the Precise Runahead (HPCA'20) in gem5☆15Oct 5, 2023Updated 2 years ago
- Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast See…☆11Feb 5, 2018Updated 8 years ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理☆152Apr 30, 2026Updated 4 months ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆14Aug 23, 2024Updated 2 years ago
- Polar codes are error correction codes developed by Erdal Arikan which achieves channel capacity and its reduced complexity makes it more…☆20Jul 22, 2021Updated 5 years ago
- Integrated Circuit Design Contest (ICDC) - 大學院校積體電路設計競賽☆25Apr 20, 2022Updated 4 years ago
- ☆13Apr 16, 2022Updated 4 years ago