openhwgroup / cvw-arch-verifLinks
The purpose of the repo is to support CORE-V Wally architectural verification
☆14Updated last week
Alternatives and similar repositories for cvw-arch-verif
Users that are interested in cvw-arch-verif are comparing it to the libraries listed below
Sorting:
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
 - Advanced Architecture Labs with CVA6☆69Updated last year
 - Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
 - Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆26Updated last year
 - SystemVerilog Functional Coverage for RISC-V ISA☆31Updated 5 months ago
 - The RTL source for AnyCore RISC-V☆32Updated 3 years ago
 - A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
 - Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
 - ☆10Updated 3 years ago
 - DUTH RISC-V Superscalar Microprocessor☆31Updated last year
 - RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆44Updated this week
 - North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago
 - RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated 2 months ago
 - ☆30Updated last week
 - IOPMP IP☆21Updated 3 months ago
 - Complete tutorial code.☆21Updated last year
 - Open source RTL simulation acceleration on commodity hardware☆30Updated 2 years ago
 - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 months ago
 - Platform Level Interrupt Controller☆43Updated last year
 - A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆25Updated 3 years ago
 - Simple UVM environment for experimenting with Verilator.☆28Updated this week
 - LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆17Updated last week
 - Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 weeks ago
 - DUTH RISC-V Microprocessor☆22Updated 10 months ago
 - Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
 - Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆31Updated 3 years ago
 - Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
 - RISC-V Nox core☆68Updated 3 months ago
 - ☆99Updated 2 years ago
 - Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago