Alternatives and similar repositories for cvw-arch-verif

Users that are interested in cvw-arch-verif are comparing it to the libraries listed below

• Youssefmdany / RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDS
  RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS
  ☆11Updated 11 months ago
• RClabiisc / I2SRV64-SS-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆23Updated last year
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆14Updated last year
• pulp-platform / axi_llc
  ☆30Updated 2 weeks ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆16Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last month
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated 3 weeks ago
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆27Updated 3 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• arhamhashmi01 / rv32i-pipeline-processor
  This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
  ☆15Updated 5 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago
• IUST-Computer-Organization / LUMOS
  Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
  ☆48Updated 7 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 9 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆30Updated 2 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆87Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆28Updated 2 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 4 years ago
• aignacio / nox
  RISC-V Nox core
  ☆66Updated 2 weeks ago
• pulp-platform / svase
  ☆32Updated 7 months ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 4 years ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆28Updated last month
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated this week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆51Updated 5 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 8 months ago
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆21Updated last year
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆23Updated last year
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆38Updated last month
• 0ctobyte / procyon
  Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.
  ☆12Updated 2 years ago