abdelazeem201 / ASIC-implementation-of-AESView external linksLinks
Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encrypti…
☆22Apr 15, 2021Updated 4 years ago
Alternatives and similar repositories for ASIC-implementation-of-AES
Users that are interested in ASIC-implementation-of-AES are comparing it to the libraries listed below
Sorting:
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆17Dec 16, 2017Updated 8 years ago
- ☆27Feb 27, 2021Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Dec 3, 2023Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆12Jul 28, 2021Updated 4 years ago
- AES-128 Encryption☆10Jul 17, 2014Updated 11 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- ☆18Jun 3, 2019Updated 6 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Mar 5, 2017Updated 8 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆23Jul 12, 2023Updated 2 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 8 years ago
- C++ and Verilog to implement AES128☆24Apr 30, 2018Updated 7 years ago
- This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) al…☆17May 2, 2013Updated 12 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 5 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆30Nov 2, 2023Updated 2 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆129Jul 31, 2022Updated 3 years ago
- EE 287 2012 Fall☆32Mar 11, 2013Updated 12 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆32Sep 24, 2018Updated 7 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated 8 months ago
- I2S transciever implemented in Verilog HDL☆32Oct 11, 2017Updated 8 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Dec 10, 2021Updated 4 years ago
- FIR band-pass filter using Verilog HDL.☆12Sep 6, 2020Updated 5 years ago
- A CircuitPython driver class for the NAU7802 24-bit ADC☆13Oct 20, 2025Updated 3 months ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- Converting Boolean expressions to CMOS Circuits☆11Oct 6, 2020Updated 5 years ago
- Design of BandGapReference Circuit using Sky130 PDK☆11Oct 30, 2021Updated 4 years ago
- DMA Project using Verilog HDL☆13Dec 26, 2019Updated 6 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆11Jan 14, 2024Updated 2 years ago
- This place provide different SRAM cells netlist to be simulated with HSpice tool in sub-20nm FinFET technologies.☆12Dec 31, 2020Updated 5 years ago
- 基于FPGA的FFT算法并行优化☆12Mar 7, 2024Updated last year
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- ☆10Jan 12, 2026Updated last month
- The Soldier Health Monitoring and Position Tracking System allows the military personnel to track the current GPS position of a soldier a…☆11Dec 27, 2021Updated 4 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆465Jul 18, 2025Updated 6 months ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 6 years ago
- Lecture Material on Deep Learning Inference using FPGA☆12Jun 9, 2020Updated 5 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Nov 4, 2022Updated 3 years ago
- Accelerate multihead attention transformer model using HLS for FPGA☆11Dec 7, 2023Updated 2 years ago