Various caches written in Verilog-HDL
☆128Apr 24, 2015Updated 10 years ago
Alternatives and similar repositories for Verilog-caches
Users that are interested in Verilog-caches are comparing it to the libraries listed below
Sorting:
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆42Oct 23, 2016Updated 9 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆45Jun 13, 2023Updated 2 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- Simple cache design implementation in verilog☆55Nov 20, 2023Updated 2 years ago
- Verilog Configurable Cache☆193Mar 9, 2026Updated last week
- A Verilog implementation of a processor cache.☆37Dec 29, 2017Updated 8 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- Implementation of Direct-Mapped-Cache to hold 256 blocks, 16 32-bit instruction/Data per block with 32-bit address line☆14Dec 29, 2018Updated 7 years ago
- ☆13Apr 1, 2017Updated 8 years ago
- Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog☆20Mar 11, 2021Updated 5 years ago
- Two Level Cache Controller implementation in Verilog HDL☆60Jul 9, 2020Updated 5 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Jul 4, 2014Updated 11 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- Verilog AXI components for FPGA implementation☆1,987Feb 27, 2025Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- ☆18Jun 3, 2019Updated 6 years ago
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- SystemVerilog VIP for AMBA APB protocol☆87Nov 11, 2021Updated 4 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- Mathematical Functions in Verilog☆97Mar 7, 2021Updated 5 years ago
- ☆19Aug 11, 2022Updated 3 years ago
- ☆11May 31, 2016Updated 9 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- 32-bit Superscalar RISC-V CPU☆1,197Sep 18, 2021Updated 4 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Apr 15, 2018Updated 7 years ago
- AXI4 BFM in Verilog☆36Dec 13, 2016Updated 9 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- Implementation of the PCIe physical layer☆61Jul 11, 2025Updated 8 months ago
- Verification IP for UART protocol☆22Aug 3, 2020Updated 5 years ago
- ☆14Feb 24, 2025Updated last year
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆24Jul 20, 2023Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- AMBA bus generator including AXI, AHB, and APB☆120Jul 29, 2021Updated 4 years ago
- AXI X-Bar☆19Apr 8, 2020Updated 5 years ago