avidan-efody / pyreg
Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python
☆10Updated 2 years ago
Alternatives and similar repositories for pyreg:
Users that are interested in pyreg are comparing it to the libraries listed below
- APB UVC ported to Verilator☆11Updated last year
- Python interface for cross-calling with HDL☆32Updated last month
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆12Updated 10 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆24Updated 2 months ago
- SystemVerilog Linter based on pyslang☆30Updated 4 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated last year
- Open-Source Framework for Co-Emulation☆11Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ☆10Updated last year
- ☆15Updated 5 years ago
- ☆31Updated 3 months ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆23Updated 4 years ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last week
- Import and export IP-XACT XML register models☆34Updated 6 months ago
- A mock framework for use with SVUnit☆18Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 11 months ago
- Generates a SystemVerilog assertion interface for a given SV RTL design☆16Updated last month
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- ☆26Updated last year
- IP-XACT XML binding library☆15Updated 8 years ago
- SystemVerilog FSM generator☆30Updated last year
- Making cocotb testbenches that bit easier☆29Updated last month
- Generate address space documentation HTML from compiled SystemRDL input☆51Updated last week
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Updated 4 months ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆22Updated 4 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆29Updated this week