avidan-efody / pyregLinks
Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python
☆11Updated 2 years ago
Alternatives and similar repositories for pyreg
Users that are interested in pyreg are comparing it to the libraries listed below
Sorting:
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Open-Source Framework for Co-Emulation☆12Updated 4 years ago
- ☆15Updated 6 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆12Updated 10 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆28Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- APB UVC ported to Verilator☆11Updated last year
- SystemVerilog Linter based on pyslang☆31Updated 3 months ago
- ☆10Updated last year
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆46Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆25Updated 4 years ago
- Python interface for cross-calling with HDL☆35Updated 2 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated this week
- Python Tool for UVM Testbench Generation☆53Updated last year
- A mock framework for use with SVUnit☆18Updated 2 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- Contains source code for sin/cos table verification using UVM☆20Updated 4 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- SystemVerilog Logger☆18Updated 2 years ago
- ☆44Updated 5 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 5 years ago
- Open Source PHY v2☆29Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 8 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆38Updated 2 months ago