Digital Design Equivalence Checking
☆78Jul 20, 2026Updated this week
Alternatives and similar repositories for kepler-formal
Users that are interested in kepler-formal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTLMeter benchmark suite☆31Jul 10, 2026Updated last week
- Netlist API (and more) for EDA flow development☆149Updated this week
- A collection of datapath circuit design and verification benchmarks☆19Jul 9, 2026Updated last week
- ☆37Updated this week
- Self-contained RTL to GDS flow for simple chip designs☆73Jul 7, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog design elaborator into word-level netlist form☆238Updated this week
- [WIP] Open-source DFT flow☆40May 9, 2026Updated 2 months ago
- ☆119Updated this week
- open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists☆41Jun 4, 2026Updated last month
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆60Jun 7, 2026Updated last month
- A Python package for creating and solving constrained randomization problems.☆19Updated this week
- ☆46Updated this week
- Expose what functional RTL benchmarks leave unanswered. Evidence profiles for AI-generated RTL; research collaborators and design partner…☆16Updated this week
- A standalone structural (gate-level) verilog parser☆41Updated this week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)☆80Updated this week
- SPARX: An Open-Source, Automated, Programmatically Generated, Frequency-Scalable Six-Port Receiver in 130-nm CMOS☆24Updated this week
- ☆24Updated this week
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago
- Blender GDSII Importer with PDK Support☆134Updated this week
- SystemVerilog compiler and language services☆1,089Updated this week
- ARCH hardware description language and compiler☆50Updated this week
- SpiceBind – spice inside HDL simulator☆58Jun 30, 2025Updated last year
- The HW-CBMC and EBMC Model Checkers for Verilog☆110Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Making cocotb testbenches that bit easier☆40Feb 28, 2026Updated 4 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆40Jan 13, 2023Updated 3 years ago
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 4 months ago
- Open-source RTL logic simulator with CUDA acceleration☆287Sep 30, 2025Updated 9 months ago
- Custom IC Design Platform☆106Updated this week
- LLM-Assisted Hardware Formal Verification Tool☆111Jul 13, 2026Updated last week
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆21Jun 14, 2026Updated last month
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆279Updated this week
- Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively☆25Updated this week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- An implementation of RISC-V☆54Jul 14, 2026Updated last week
- ☆63Mar 31, 2025Updated last year
- Coverview☆31Jun 3, 2026Updated last month
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year
- Waveform Viewer Extension for VScode☆348Jul 14, 2026Updated last week
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 5 months ago
- A Chip Design Automation Solution with Open Source EDA Tools.☆15Updated this week