Digital Design Equivalence Checking
☆101Aug 28, 2026Updated this week
Alternatives and similar repositories for kepler-formal
Users that are interested in kepler-formal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Netlist API (and more) for EDA flow development☆160Updated this week
- RTLMeter benchmark suite☆32Updated this week
- Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract☆23Aug 12, 2026Updated 2 weeks ago
- A collection of datapath circuit design and verification benchmarks☆19Updated this week
- ☆39Jul 23, 2026Updated last month
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Self-contained RTL to GDS flow for simple chip designs☆76Jul 7, 2026Updated last month
- SystemVerilog design elaborator into word-level netlist form☆249Updated this week
- A novel Design-for-Test flow using LibreLane☆46May 9, 2026Updated 3 months ago
- ☆127Aug 21, 2026Updated last week
- open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists☆42Updated this week
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆60Aug 19, 2026Updated last week
- A Python package for creating and solving constrained randomization problems.☆19Aug 10, 2026Updated 2 weeks ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆114Updated this week
- ☆47Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Expose what functional RTL benchmarks leave unanswered. Evidence profiles for AI-generated RTL; research collaborators and design partner…☆20Updated this week
- A standalone structural (gate-level) verilog parser☆42Jul 29, 2026Updated last month
- Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)☆83Aug 10, 2026Updated 2 weeks ago
- SPARX: An Open-Source, Automated, Programmatically Generated, Frequency-Scalable Six-Port Receiver in 130-nm CMOS☆34Updated this week
- ☆25Updated this week
- Making cocotb testbenches that bit easier☆42Feb 28, 2026Updated 6 months ago
- Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively☆43Aug 14, 2026Updated 2 weeks ago
- SystemVerilog file list pruner☆19Updated this week
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Blender GDSII Importer with PDK Support☆139Updated this week
- SystemVerilog compiler and language services☆1,124Updated this week
- ARCH hardware description language and compiler☆74Updated this week
- SpiceBind – spice inside HDL simulator☆58Aug 14, 2026Updated 2 weeks ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆44Jan 13, 2023Updated 3 years ago
- Open-source RTL logic simulator with CUDA acceleration☆294Sep 30, 2025Updated 10 months ago
- Custom IC Design Platform☆115Updated this week
- Hardware Formal Verification Tool☆114Jul 13, 2026Updated last month
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆24Jun 14, 2026Updated 2 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Python interface for cross-calling with HDL☆52Mar 14, 2026Updated 5 months ago
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆286Updated this week
- An implementation of RISC-V☆54Jul 14, 2026Updated last month
- Curriculum for a university course to teach chip design using open source EDA tools☆163Oct 21, 2023Updated 2 years ago
- ☆65Mar 31, 2025Updated last year
- Coverview☆33Updated this week
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year