The-OpenROAD-Project / megaboomLinks
☆25Updated this week
Alternatives and similar repositories for megaboom
Users that are interested in megaboom are comparing it to the libraries listed below
Sorting:
- SystemVerilog RTL Linter for YoSys☆20Updated 6 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆69Updated 4 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆19Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- Library of open source Process Design Kits (PDKs)☆42Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- Open source process design kit for 28nm open process☆56Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆16Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆62Updated 2 years ago
- ☆41Updated 3 years ago
- Logic synthesis and ABC based optimization☆49Updated 3 weeks ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆15Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆36Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- Open Source PHY v2☆28Updated last year
- RISC-V Nox core☆62Updated 2 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated this week
- APB UVC ported to Verilator☆11Updated last year
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆110Updated 2 weeks ago
- Complete tutorial code.☆20Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- ☆32Updated 4 months ago
- ☆44Updated 5 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year