The-OpenROAD-Project / megaboomLinks
☆27Updated last week
Alternatives and similar repositories for megaboom
Users that are interested in megaboom are comparing it to the libraries listed below
Sorting:
- SystemVerilog RTL Linter for YoSys☆20Updated 7 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆70Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆45Updated 3 years ago
- ☆41Updated 3 years ago
- Open source process design kit for 28nm open process☆59Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆61Updated 5 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆63Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- Introductory course into static timing analysis (STA).☆95Updated 2 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆19Updated 2 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 7 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 4 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated this week
- An automatic clock gating utility☆49Updated 2 months ago
- Library of open source Process Design Kits (PDKs)☆47Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆113Updated last week
- APB UVC ported to Verilator☆11Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated this week
- Logic synthesis and ABC based optimization☆49Updated 2 weeks ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- ☆44Updated 5 years ago