Alternatives and similar repositories for Parser-Verilog

Users that are interested in Parser-Verilog are comparing it to the libraries listed below

• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 5 months ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆102Updated 3 years ago
• parallaxsw / OpenSTA
  ☆97Updated last week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆173Updated 3 months ago
• pkuzjx / eda-collection
  ☆107Updated 6 years ago
• ncsu-eda / FreePDK3
  ☆183Updated 4 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆63Updated 4 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆80Updated 4 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆54Updated last year
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆51Updated 3 weeks ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆38Updated 2 years ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆28Updated 4 years ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆195Updated 5 years ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated 3 years ago
• liyanqing1987 / libertyParser
  liberty parser (For parsing IC timing lib file)
  ☆65Updated 2 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated this week
• The-OpenROAD-Project / asap7
  ☆218Updated 9 months ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆115Updated 5 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆135Updated last month
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆89Updated 7 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆275Updated 2 weeks ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆111Updated 2 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated 3 weeks ago
• ABKGroup / PROBE3.0
  ☆49Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆184Updated this week
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆78Updated 5 years ago
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆43Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated last month
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆74Updated 3 weeks ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆69Updated last year