A Standalone Structural Verilog Parser
☆99Mar 31, 2022Updated 3 years ago
Alternatives and similar repositories for Parser-Verilog
Users that are interested in Parser-Verilog are comparing it to the libraries listed below
Sorting:
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆59Aug 7, 2022Updated 3 years ago
- A standalone structural (gate-level) verilog parser☆40Feb 2, 2026Updated last month
- A verilog parser☆19Apr 12, 2024Updated last year
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.☆135Jul 17, 2019Updated 6 years ago
- This is the Verilog 2005 parser used by VerilogCreator☆15May 19, 2019Updated 6 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆691Dec 26, 2025Updated 2 months ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆135Updated this week
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- Open Source Detailed Placement engine☆12Feb 19, 2020Updated 6 years ago
- Mirror of Synopsys's Liberty parser library☆24Jul 6, 2018Updated 7 years ago
- A LEF/DEF Utility.☆34Aug 15, 2019Updated 6 years ago
- Problems and Results of IWLS 2022 Programming Contest☆22Apr 12, 2025Updated 11 months ago
- UCSD Detailed Router☆95Jan 5, 2021Updated 5 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆194May 19, 2025Updated 10 months ago
- Tools for working with circuits as graphs in python☆126Nov 17, 2023Updated 2 years ago
- discrete gate sizing☆14Nov 23, 2020Updated 5 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆142Mar 20, 2023Updated 3 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- NTHU CS6135 VLSI Physical Design Automation (2022 Fall)☆19Jan 20, 2023Updated 3 years ago
- A complete open-source design-for-testing (DFT) Solution☆182Aug 30, 2025Updated 6 months ago
- A simple dot file / graph generator for Verilog syntax trees.☆23Jul 16, 2016Updated 9 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆320Jun 30, 2025Updated 8 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆368Updated this week
- GT3 PDK☆24Nov 14, 2025Updated 4 months ago
- Deep learning toolkit-enabled VLSI placement☆961Feb 19, 2026Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆451Mar 8, 2026Updated 2 weeks ago
- EPWave -- The Free Interactive Browser-Based Wave Viewer☆14Apr 1, 2015Updated 10 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆20Aug 20, 2019Updated 6 years ago
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆24Feb 24, 2026Updated 3 weeks ago
- GPU-based logic synthesis tool☆100Nov 27, 2025Updated 3 months ago
- Open Source Detailed Placement engine☆40Nov 27, 2019Updated 6 years ago
- Database and Tool Framework for EDA☆123Jan 25, 2021Updated 5 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆18Feb 22, 2026Updated last month
- The first version of TritonPart☆33Jan 2, 2024Updated 2 years ago
- Macro placement tool for OpenROAD flow☆25Aug 13, 2020Updated 5 years ago
- OpenSTA engine☆555Updated this week
- Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"☆27Dec 9, 2018Updated 7 years ago