Alternatives and similar repositories for Parser-Verilog

Users that are interested in Parser-Verilog are comparing it to the libraries listed below

• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆100Updated 3 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆98Updated 3 months ago
• parallaxsw / OpenSTA
  ☆90Updated this week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated last month
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆51Updated last year
• lnis-uofu / LSOracle
  IDEA project source files
  ☆108Updated last week
• The-OpenROAD-Project / asap7
  ☆201Updated 7 months ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated 2 years ago
• ncsu-eda / FreePDK3
  ☆178Updated 4 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆79Updated 4 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆64Updated 9 months ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆112Updated 4 years ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆191Updated 5 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆127Updated last month
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆269Updated last week
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆82Updated last year
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆158Updated 3 weeks ago
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆50Updated 2 weeks ago
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆133Updated 6 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆166Updated last week
• liyanqing1987 / libertyParser
  liberty parser (For parsing IC timing lib file)
  ☆65Updated 2 years ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆85Updated 5 months ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆62Updated last year
• pkuzjx / eda-collection
  ☆106Updated 5 years ago
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆96Updated 3 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆65Updated this week