SystemVerilog (IEEE 1800-2017) Simulator
☆69Aug 3, 2026Updated this week
Alternatives and similar repositories for xezim
Users that are interested in xezim are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year
- Reflection API for SystemVerilog☆14Mar 30, 2026Updated 4 months ago
- ☆46Updated this week
- Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)☆82Updated this week
- Parse FSDB waveform files☆23Apr 13, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RTLMeter benchmark suite☆31Jul 21, 2026Updated last week
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- ☆10May 27, 2026Updated 2 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆132Updated this week
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆20Jul 28, 2025Updated last year
- Python interface for cross-calling with HDL☆51Mar 14, 2026Updated 4 months ago
- VS Code extension for SystemVerilog design navigation, RTL tracing, schematic viewer, and waveform integration☆58Jul 25, 2026Updated last week
- SystemVerilog file list pruner☆18Updated this week
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Aug 7, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17Jun 5, 2024Updated 2 years ago
- ☆20Jul 28, 2026Updated last week
- SystemVerilog wrapper over the Verilog Programming Interface (VPI)☆12Jun 3, 2025Updated last year
- Making cocotb testbenches that bit easier☆41Feb 28, 2026Updated 5 months ago
- A SystemVerilog language server based on the Slang library.☆288Updated this week
- Simple template-based UVM code generator☆30Apr 15, 2026Updated 3 months ago
- LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framew…☆29Jul 6, 2026Updated 3 weeks ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated last month
- Python packages providing a library for Verification Stimulus and Coverage☆147Jul 5, 2026Updated 3 weeks ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated last year
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆60Jun 7, 2026Updated last month
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆137Jul 21, 2026Updated 2 weeks ago
- SpiceBind – spice inside HDL simulator☆58Jun 30, 2025Updated last year
- fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI☆100Jul 19, 2026Updated 2 weeks ago
- Communication framework for RTL simulation and emulation.☆315Jul 27, 2026Updated last week
- Digital Design Equivalence Checking☆89Updated this week
- VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…☆31Oct 5, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- みんなのSystemVerilog☆19May 12, 2022Updated 4 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- A library and command-line tool for querying a Verilog netlist.☆30Jun 13, 2022Updated 4 years ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago
- [WIP] Open-source DFT flow☆41May 9, 2026Updated 2 months ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆49Jul 11, 2025Updated last year