Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)
☆78Jul 14, 2026Updated this week
Alternatives and similar repositories for Jacquard
Users that are interested in Jacquard are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Characterizer☆38Jun 26, 2026Updated 2 weeks ago
- ☆21Oct 20, 2025Updated 8 months ago
- SpiceBind – spice inside HDL simulator☆58Jun 30, 2025Updated last year
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆77Updated this week
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆63Mar 13, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- LibreLane full-chip flow template for IHP SG13G2 OpenPDK☆19Apr 20, 2026Updated 2 months ago
- SystemVerilog (IEEE 1800-2017) Simulator☆60Updated this week
- C++ HDL (Hardware Description Language)☆48Updated this week
- IHP Open source SG13G2 Tape Out on April 2025 [Testfield T586]☆17Apr 27, 2026Updated 2 months ago
- RTLMeter benchmark suite☆31Updated this week
- An Open-Source ASIC Design Template for the SG13G2 IHP Open-PDK☆21Updated this week
- Parasitic capacitance analysis of foundry metal stackups☆18Jan 12, 2026Updated 6 months ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 11 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆107Jul 1, 2026Updated last week
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- RFIC EM simulation: Create AWS Palace model from GDSII layout files☆53Updated this week
- Open-source PDK version manager☆55Updated this week
- Reinforcement learning assisted analog layout design flow.☆38Jul 29, 2024Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆251Jun 30, 2026Updated 2 weeks ago
- fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI☆93Updated this week
- photonSDI - an open source SDI core☆11May 26, 2021Updated 5 years ago
- FPGA synthesis tool powered by program synthesis☆56Dec 15, 2025Updated 6 months ago
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 6 years ago
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆25Feb 15, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Aug 28, 2025Updated 10 months ago
- A bit-serial CPU☆20Sep 29, 2019Updated 6 years ago
- An Open-Source Analog Mixed-Signal Chip Design Template & Tutorial for the ihp-sg13g2 Open-PDK☆22Updated this week
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆93Dec 18, 2024Updated last year
- Advanced Integrated Circuits 2024☆24Nov 16, 2024Updated last year
- COCOA: Collaborative Compendium on Analog Integrated Circuits☆29Jan 14, 2026Updated 6 months ago
- Administrative repository for the Integrated Matrix Extension Task Group☆36Apr 25, 2026Updated 2 months ago
- ☆15Feb 6, 2021Updated 5 years ago
- Expose what functional RTL benchmarks leave unanswered. Evidence profiles for AI-generated RTL; research collaborators and design partner…☆15Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆38Apr 9, 2026Updated 3 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆76Feb 12, 2026Updated 5 months ago
- ☆63Mar 31, 2025Updated last year
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆23Jun 19, 2026Updated 3 weeks ago
- ☆118Updated this week
- SDI interface board for the apertus° AXIOM beta camera☆13Jan 19, 2019Updated 7 years ago
- LunaPnR is a place and router for integrated circuits☆48Feb 11, 2026Updated 5 months ago