muhammadaldacher / Layout-Design-of-an-8x8-SRAM-arrayLinks
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.
☆80Updated 3 years ago
Alternatives and similar repositories for Layout-Design-of-an-8x8-SRAM-array
Users that are interested in Layout-Design-of-an-8x8-SRAM-array are comparing it to the libraries listed below
Sorting:
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆183Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆80Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆91Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆43Updated 3 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆48Updated last year
- ☆183Updated 4 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆35Updated 6 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆193Updated this week
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆52Updated 4 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆191Updated 5 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆78Updated 2 years ago
- Introductory course into static timing analysis (STA).☆99Updated 4 months ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆24Updated last year
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆168Updated 3 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆166Updated last month
- ☆208Updated 8 months ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- This repo provide an index of VLSI content creators and their materials☆160Updated last year
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- ☆43Updated 3 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆112Updated 2 years ago
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆224Updated 2 months ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆14Updated last year
- Solve one design problem each day for a month☆49Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆101Updated 2 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆37Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year