aieask / mdw21Links
Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis
☆18Updated 3 years ago
Alternatives and similar repositories for mdw21
Users that are interested in mdw21 are comparing it to the libraries listed below
Sorting:
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆83Updated 3 years ago
- This place provide different SRAM cells netlist to be simulated with HSpice tool in sub-20nm FinFET technologies.☆12Updated 5 years ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆174Updated 5 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆202Updated 3 weeks ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆189Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆103Updated last year
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆55Updated 8 years ago
- Implementing Different Adder Structures in Verilog☆74Updated 6 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Updated last year
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- RTL to GDS via Cadence Tools☆16Updated 3 years ago
- ☆189Updated 4 years ago
- ☆234Updated 10 months ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆54Updated last year
- ☆15Updated 2 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆25Updated last year
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆201Updated 5 years ago
- ☆86Updated last year
- UVM and System Verilog Manuals☆48Updated 6 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆45Updated 3 years ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆77Updated 3 years ago
- This is a tutorial on standard digital design flow☆83Updated 4 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆108Updated 2 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆133Updated 2 years ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆107Updated 7 months ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆41Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆25Updated 7 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆31Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago