This project shows the design process of the main blocks of a typical RX frontend system.
☆31Jan 2, 2021Updated 5 years ago
Alternatives and similar repositories for RF-design-of-1.9-GHz-Rx-frontend
Users that are interested in RF-design-of-1.9-GHz-Rx-frontend are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆45Mar 2, 2022Updated 4 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆95Jun 12, 2023Updated 3 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆15Jan 2, 2021Updated 5 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆34Feb 21, 2019Updated 7 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆17Sep 12, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆26May 2, 2025Updated last year
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆234Nov 13, 2024Updated last year
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆13Jul 8, 2019Updated 7 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆21Apr 20, 2019Updated 7 years ago
- Advanced integrated circuits 2023☆36Feb 25, 2024Updated 2 years ago
- Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC☆29Jun 12, 2018Updated 8 years ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆19Nov 29, 2020Updated 5 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆21Dec 15, 2020Updated 5 years ago
- Solve one design problem each day for a month☆56Feb 3, 2023Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- repository for a bandgap voltage reference in SKY130 technology☆45Jan 20, 2023Updated 3 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆42Jun 10, 2021Updated 5 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆96Mar 19, 2026Updated 5 months ago
- A current mode buck converter on the SKY130 PDK☆39Jun 17, 2021Updated 5 years ago
- Open Analog Design Environment☆26May 19, 2023Updated 3 years ago
- Collection of various Jupyter and Quarto notebooks related to the design of CMOS analog integrated circuits☆34Aug 19, 2026Updated 2 weeks ago
- ☆24Dec 8, 2021Updated 4 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆28Mar 11, 2023Updated 3 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆126Jul 31, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- BAG (BAG AMS Generator) Primitives Library for SKY130☆22May 16, 2023Updated 3 years ago
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 3 years ago
- ☆13Apr 22, 2021Updated 5 years ago
- PLL Designs on Skywater 130nm MPW☆25Dec 3, 2023Updated 2 years ago
- 9-bit SAR in skywater 130 nm☆18Jan 15, 2025Updated last year
- Files for Advanced Integrated Circuits☆45Aug 6, 2026Updated last month
- Fundamental analog circuit designs to kick start and embark the journey in the world of IC design.☆35Aug 31, 2023Updated 3 years ago
- A Python and SKILL Framework for Cadence Virtuoso☆57Dec 13, 2025Updated 8 months ago
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆32Jun 13, 2015Updated 11 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆32May 30, 2024Updated 2 years ago
- Simple and most probably incomplete parser for spectre netlists☆14Oct 4, 2016Updated 9 years ago
- Ten Thousand Failures Blog☆12Jul 22, 2014Updated 12 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆75Oct 4, 2021Updated 4 years ago
- ☆13Jan 25, 2023Updated 3 years ago
- ☆12Dec 11, 2023Updated 2 years ago
- ☆172Dec 4, 2022Updated 3 years ago