muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-systemLinks
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
☆71Updated 2 years ago
Alternatives and similar repositories for Analog-Design-of-1.9-GHz-PLL-system
Users that are interested in Analog-Design-of-1.9-GHz-PLL-system are comparing it to the libraries listed below
Sorting:
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆174Updated 10 months ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆96Updated 4 months ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆34Updated 3 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆159Updated last month
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆75Updated 3 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆32Updated 6 years ago
- Solve one design problem each day for a month☆46Updated 2 years ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆164Updated last month
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆82Updated last year
- repository for a bandgap voltage reference in SKY130 technology☆40Updated 2 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆14Updated 6 years ago
- A python3 gm/ID starter kit☆52Updated last month
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆47Updated 5 years ago
- Advanced integrated circuits 2023☆32Updated last year
- ☆84Updated 8 months ago
- A 10bit SAR ADC in Sky130☆25Updated 2 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆12Updated 6 years ago
- PLL Designs on Skywater 130nm MPW☆21Updated last year
- ☆102Updated last month
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆77Updated 4 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆188Updated 4 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆48Updated 4 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆99Updated last year
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆56Updated last week
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆213Updated 3 weeks ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆71Updated 5 months ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 8 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆43Updated 3 years ago