Alternatives and similar repositories for 4-bit-cpu

Users that are interested in 4-bit-cpu are comparing it to the libraries listed below

• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• esmil / riscv-linux
  Getting started running RISC-V Linux
  ☆18Updated 4 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆154Updated last year
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆53Updated 8 months ago
• s-holst / tinyrv
  A tiny RISC-V instruction decoder and instruction set simulator
  ☆33Updated 3 months ago
• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆17Updated 3 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆105Updated 9 months ago
• Ashwin-Rajesh / RiSC-16
  RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…
  ☆12Updated 4 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆114Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆76Updated 2 years ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆142Updated 2 years ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆88Updated this week
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆64Updated last year
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆49Updated 3 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆39Updated last month
• AngeloJacobo / FPGA_Asynchronous_FIFO
  FIFO implementation with different clock domains for read and write.
  ☆14Updated 4 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆98Updated last week
• Ashwin-Rajesh / Verilog_projects
  Some beginner projects using verilog HDL, along with some documentation on basic syntax
  ☆13Updated 4 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 3 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆82Updated 10 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 2 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆49Updated last month
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆101Updated 2 months ago
• riscv-non-isa / riscv-external-debug-security
  The RISC-V External Debug Security Specification
  ☆20Updated last week
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆81Updated 2 weeks ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆79Updated 3 years ago
• jaywonchung / Verilog-Harvard-CPU
  Verilog implementation of various types of CPUs
  ☆73Updated 6 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 4 years ago