Alternatives and similar repositories for 4-bit-cpu

Users that are interested in 4-bit-cpu are comparing it to the libraries listed below

• ecilasun / e32e
  Latest in the line of the E32 processors with better/generic cache placement
  ☆10Updated 2 years ago
• esmil / riscv-linux
  Getting started running RISC-V Linux
  ☆18Updated 4 years ago
• AngeloJacobo / FPGA_Asynchronous_FIFO
  FIFO implementation with different clock domains for read and write.
  ☆14Updated 4 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• Ashwin-Rajesh / Verilog_projects
  Some beginner projects using verilog HDL, along with some documentation on basic syntax
  ☆12Updated 4 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 3 years ago
• efabless / mpw_precheck
  ☆43Updated 7 months ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 11 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆97Updated 5 months ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆63Updated last week
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆34Updated last year
• efabless / caravel_board
  ☆36Updated 10 months ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• dominiksalvet / risc63
  Custom 64-bit pipelined RISC processor
  ☆17Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 11 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 4 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆61Updated last week
• olofk / corescore
  CoreScore
  ☆163Updated last month
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 5 years ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆49Updated 4 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆13Updated 3 years ago
• Ashwin-Rajesh / RiSC-16
  RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…
  ☆12Updated 3 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆116Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 6 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆95Updated this week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• TinyTapeout / tt06-verilog-template
  Submission template for Tiny Tapeout 6 - Verilog HDL Projects
  ☆34Updated last year
• pascalkuthe / OpenVAF
  An innovative Verilog-A compiler
  ☆166Updated last year
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆83Updated last week