Schematic, Layout Design & Simulation in 180nm Technology
☆22Nov 21, 2020Updated 5 years ago
Alternatives and similar repositories for Cadence_Virtuoso_180nm_Projects
Users that are interested in Cadence_Virtuoso_180nm_Projects are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆38Mar 22, 2019Updated 7 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆18Apr 20, 2019Updated 6 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆14Mar 17, 2019Updated 7 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆29Feb 21, 2019Updated 7 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆42Mar 2, 2022Updated 4 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆25Jul 9, 2025Updated 8 months ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆198Nov 13, 2024Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆87Mar 19, 2026Updated last week
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆24May 2, 2025Updated 10 months ago
- Fundamental analog circuit designs to kick start and embark the journey in the world of IC design.☆33Aug 31, 2023Updated 2 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆15Dec 8, 2020Updated 5 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆82Jun 12, 2023Updated 2 years ago
- ☆17Sep 19, 2022Updated 3 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆37Apr 7, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Go Board FPGA Project for Ambient Light Sensor in VHDL and Verilog☆10Apr 20, 2019Updated 6 years ago
- A collection of commonly asked RTL design interview questions☆39May 2, 2017Updated 8 years ago
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆56Dec 16, 2025Updated 3 months ago
- The GATE EC Preparation Repository provides comprehensive study materials, including handbooks, formula books, solved papers (2010-2024),…☆31Jul 18, 2025Updated 8 months ago
- Integrated Circuit Design - IC Design Flow and Project-Based Learning☆50Mar 1, 2026Updated 3 weeks ago
- This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK …☆14Dec 15, 2023Updated 2 years ago
- Vitis-AI 1.3 TensorFlow2 flow with a custom CNN model, targeted ZCU102 evaluation board.☆15Apr 6, 2021Updated 4 years ago
- Verilog Project☆21Aug 30, 2021Updated 4 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆13Jun 13, 2021Updated 4 years ago
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- ☆26May 27, 2025Updated 10 months ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆13Mar 30, 2023Updated 3 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14May 11, 2014Updated 11 years ago
- UART in Verilog and VHDL☆18Aug 21, 2022Updated 3 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Jul 14, 2019Updated 6 years ago
- Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.☆14Nov 29, 2018Updated 7 years ago
- 丁建均老師的"時頻分析和小波轉換"作業(TFW)☆11Jan 18, 2024Updated 2 years ago
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- Motion Estimation implementation by using Verilog HDL☆13Jun 17, 2024Updated last year
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆14Mar 3, 2023Updated 3 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- From Pytorch model to C++ for Vitis HLS☆20Mar 18, 2026Updated last week
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆46Aug 31, 2025Updated 6 months ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆15Sep 12, 2023Updated 2 years ago
- A list of helpful resources for students learning MATLAB & Simulink. List includes tips & tricks, tutorials, videos, cheat sheets, and op…☆15Mar 12, 2026Updated 2 weeks ago