rhovector / Cadence_Virtuoso_180nm_ProjectsLinks
Schematic, Layout Design & Simulation in 180nm Technology
☆22Updated 4 years ago
Alternatives and similar repositories for Cadence_Virtuoso_180nm_Projects
Users that are interested in Cadence_Virtuoso_180nm_Projects are comparing it to the libraries listed below
Sorting:
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆32Updated 6 years ago
- Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.☆14Updated 6 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆24Updated 6 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆46Updated 4 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆71Updated 2 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆32Updated 3 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago
- Hardware and Software Co-design implementations☆14Updated 5 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆19Updated 2 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆23Updated 4 years ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆14Updated 3 years ago
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆73Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Proce…☆24Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆32Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆59Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆45Updated last year
- Interface Protocol in Verilog☆50Updated 6 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆19Updated 2 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆20Updated 4 years ago
- Repository for system verilog labs from cadence☆13Updated 5 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆168Updated 8 months ago
- Ethernet MAC 10/100 Mbps☆85Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- ☆41Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆15Updated 5 years ago
- RISC-V Embedded Processor for Approximate Computing☆125Updated 2 months ago
- This repository contains some introductory level review about learning about FPGA Design including some tutorials, links to websites and …☆36Updated 4 months ago