FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130Links
This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
☆33Updated 4 years ago
Alternatives and similar repositories for eFPGA---RTL-to-GDS-with-SKY130
Users that are interested in eFPGA---RTL-to-GDS-with-SKY130 are comparing it to the libraries listed below
Sorting:
- ☆43Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- SRAM☆22Updated 5 years ago
- Open source process design kit for 28nm open process☆67Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆80Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆24Updated 6 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- Open Source PHY v2☆31Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆52Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆91Updated this week
- ☆20Updated 3 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Updated 2 years ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- ☆56Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Proce…☆28Updated 2 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- Verilog RTL Design☆45Updated 4 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Contains commonly used UVM components (agents, environments and tests).☆31Updated 7 years ago
- Completed LDO Design for Skywaters 130nm☆17Updated 2 years ago