Prananya123 / RTL-CodingLinks
☆22Updated 2 years ago
Alternatives and similar repositories for RTL-Coding
Users that are interested in RTL-Coding are comparing it to the libraries listed below
Sorting:
- ☆115Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆115Updated 3 years ago
- This repo provide an index of VLSI content creators and their materials☆156Updated last year
- 100 Days of RTL☆390Updated last year
- opensource EDA tool flor VLSI design☆33Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆90Updated 2 years ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆109Updated 11 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆22Updated this week
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆265Updated 3 months ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆24Updated last year
- ☆164Updated 2 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆17Updated 4 years ago
- Verilog HDL files☆149Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated 2 years ago
- ☆42Updated 2 years ago
- ☆15Updated 2 years ago
- ☆17Updated last year
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆64Updated 2 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆152Updated last year
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆110Updated 3 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated last year
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆23Updated 7 months ago
- SystemVerilog Tutorial☆166Updated 3 months ago
- ☆16Updated last year
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- Static Timing Analysis Full Course☆59Updated 2 years ago