Prananya123 / RTL-Coding
☆22Updated last year
Related projects ⓘ
Alternatives and complementary repositories for RTL-Coding
- ☆9Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆98Updated 2 years ago
- ☆99Updated 10 months ago
- ☆16Updated 10 months ago
- Architectural design of data router in verilog☆27Updated 4 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- This repo provide an index of VLSI content creators and their materials☆136Updated 3 months ago
- ☆13Updated 8 months ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- ☆36Updated 3 years ago
- opensource EDA tool flor VLSI design☆29Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆52Updated last year
- ☆40Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated last year
- SystemVerilog Tutorial☆114Updated 11 months ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆9Updated 7 months ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- ☆120Updated 2 years ago
- ☆15Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆19Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- ☆16Updated last year
- UVM and System Verilog Manuals☆36Updated 5 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated 5 months ago
- ☆12Updated 9 months ago