muhammadaldacher / Analog-Design-of-Asynchronous-SAR-ADCView external linksLinks
This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
☆194Nov 13, 2024Updated last year
Alternatives and similar repositories for Analog-Design-of-Asynchronous-SAR-ADC
Users that are interested in Analog-Design-of-Asynchronous-SAR-ADC are comparing it to the libraries listed below
Sorting:
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆81Jun 12, 2023Updated 2 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆39Mar 2, 2022Updated 3 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆28Feb 21, 2019Updated 6 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆24May 2, 2025Updated 9 months ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆26Jan 2, 2021Updated 5 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆15Sep 12, 2023Updated 2 years ago
- A 10bit SAR ADC in Sky130☆30Dec 4, 2022Updated 3 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆12Jul 8, 2019Updated 6 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆84Aug 7, 2022Updated 3 years ago
- Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC☆28Jun 12, 2018Updated 7 years ago
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆71Apr 9, 2018Updated 7 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆18Apr 20, 2019Updated 6 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆36Apr 7, 2019Updated 6 years ago
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆26Jun 29, 2024Updated last year
- Model SAR ADC with python!☆22Jul 8, 2022Updated 3 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆30Jul 30, 2022Updated 3 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆13Mar 17, 2019Updated 6 years ago
- Schematic, Layout Design & Simulation in 180nm Technology☆22Nov 21, 2020Updated 5 years ago
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆254Aug 21, 2025Updated 5 months ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆24May 13, 2023Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆39Jun 13, 2023Updated 2 years ago
- Simulink model for noise shaping SAR ADC☆12Mar 17, 2020Updated 5 years ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆24May 30, 2024Updated last year
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆20Dec 15, 2020Updated 5 years ago
- Digital Standard Cells based SAR ADC☆14Aug 5, 2021Updated 4 years ago
- Open Analog Design Environment☆25May 19, 2023Updated 2 years ago
- 9-bit SAR in skywater 130 nm☆17Jan 15, 2025Updated last year
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆12Jul 3, 2025Updated 7 months ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆78Oct 10, 2022Updated 3 years ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆71Feb 10, 2026Updated last week
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Jan 2, 2021Updated 5 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆11Apr 19, 2022Updated 3 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆39Jun 10, 2021Updated 4 years ago
- repository for a bandgap voltage reference in SKY130 technology☆42Jan 20, 2023Updated 3 years ago
- Fundamental analog circuit designs to kick start and embark the journey in the world of IC design.☆31Aug 31, 2023Updated 2 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆177Oct 6, 2025Updated 4 months ago
- ☆15Jun 22, 2023Updated 2 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆25Jan 10, 2022Updated 4 years ago
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆56Dec 16, 2025Updated 2 months ago