Enanter / ADPLLLinks
All Digital Phase-Locked Loop
☆12Updated 2 years ago
Alternatives and similar repositories for ADPLL
Users that are interested in ADPLL are comparing it to the libraries listed below
Sorting:
- All digital PLL☆28Updated 7 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆36Updated last year
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated last week
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Testbenches for HDL projects☆22Updated this week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- SystemVerilog FSM generator☆32Updated last year
- Test dashboard for verification features in Verilator☆28Updated this week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆40Updated last week
- Extensible FPGA control platform☆61Updated 2 years ago
- Summer School Week 1 & 2 repo☆11Updated 3 years ago
- Repository gathering basic modules for CDC purpose☆56Updated 5 years ago
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 9 months ago
- Open source process design kit for 28nm open process☆68Updated last year
- SpiceBind – spice inside HDL simulator☆56Updated 5 months ago
- Example designs for using Ethernet FMC without a processor (ie. state machine based)☆34Updated last year
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆22Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- Open FPGA Modules☆24Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆77Updated last week
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆29Updated last month
- A compact, configurable RISC-V core☆12Updated 4 months ago
- A flexible and scalable development platform for modern FPGA projects.☆38Updated 3 weeks ago
- Generate testbench for your verilog module.☆38Updated 7 years ago