All Digital Phase-Locked Loop
☆15May 22, 2023Updated 3 years ago
Alternatives and similar repositories for ADPLL
Users that are interested in ADPLL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- All digital PLL☆29Dec 19, 2017Updated 8 years ago
- All-Digital Phase-Locked Loops (ADPLL) code in High Speed Integrated Circuit Hardware Description Language (VHDL) for a Field Programmabl…☆13Oct 20, 2025Updated 10 months ago
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- SRAM build space for SKY130 provided by SkyWater.☆25Oct 20, 2021Updated 4 years ago
- FPGA based signal generator☆14Dec 25, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Solidstate relay card for Keithley DMM6500 using an STM32 microcontroller☆16Apr 11, 2021Updated 5 years ago
- KiCAD Templates for DEC FLIP CHIP Modules☆18May 11, 2022Updated 4 years ago
- PAST SHORT COURSES AND TUTORIALS FROM ISSCC.☆17Apr 7, 2024Updated 2 years ago
- ☆19Aug 26, 2016Updated 10 years ago
- VSD workshop - Phase Locked Loop(PLL) IC Design☆17Aug 4, 2021Updated 5 years ago
- understanding the tinyfpga bootloader☆25Apr 22, 2018Updated 8 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆17Apr 25, 2020Updated 6 years ago
- A collection of phase locked loop (PLL) related projects☆122Jan 18, 2024Updated 2 years ago
- MATLAB Implementation of a Digital PLL☆17Aug 15, 2016Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This is a complementary extension to the https://hub.docker.com/r/hpretl/iic-osic-tools Docker image, adding support for RF simulations a…☆17Aug 18, 2026Updated last week
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 7 years ago
- Standardised instrument control, data handling and simple GUI creation library for making experiment control programs.☆35Jun 5, 2026Updated 2 months ago
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆16Apr 14, 2026Updated 4 months ago
- ☆15Feb 24, 2019Updated 7 years ago
- Tiva Ware C Series blinky example using CMake and Visual Studio Code☆16Aug 5, 2019Updated 7 years ago
- PCA in rust☆16Jul 30, 2023Updated 3 years ago
- ☆34Nov 4, 2018Updated 7 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆24Oct 8, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆33Mar 12, 2021Updated 5 years ago
- aim to assess signal quality for heart sound signal