I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
☆29Jul 23, 2023Updated 2 years ago
Alternatives and similar repositories for 100DaysOfRtl
Users that are interested in 100DaysOfRtl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆27Jun 4, 2024Updated last year
- ☆10Oct 16, 2023Updated 2 years ago
- ☆119Dec 24, 2023Updated 2 years ago
- ☆45Jul 20, 2023Updated 2 years ago
- ☆18Feb 26, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆119Jul 9, 2023Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 2 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆20Aug 5, 2023Updated 2 years ago
- ☆11Apr 18, 2026Updated last month
- ☆16Mar 27, 2024Updated 2 years ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆40Nov 6, 2022Updated 3 years ago
- ☆24Feb 10, 2024Updated 2 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆85Oct 28, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆14Sep 27, 2022Updated 3 years ago
- ☆18Jun 12, 2023Updated 2 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- DMA Hardware Description with Verilog☆19Dec 20, 2019Updated 6 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Jan 2, 2021Updated 5 years ago
- Verilog Fundamentals Explained for Beginners and Professionals☆20Jan 15, 2023Updated 3 years ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆13Nov 19, 2023Updated 2 years ago
- Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis☆17Dec 9, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SystemVerilog examples and projects☆20Jun 10, 2025Updated 11 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆19Jul 21, 2020Updated 5 years ago
- RTL Design and Verification☆21Jan 4, 2021Updated 5 years ago
- 100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves c…☆27Apr 26, 2023Updated 3 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆67May 8, 2021Updated 5 years ago
- Single Instruction Multiple Threads GPU Core with textbook Streaming Multi-Processor features☆65Jan 30, 2026Updated 3 months ago
- AXI Interconnect☆56Aug 20, 2021Updated 4 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆64Jul 5, 2024Updated last year
- VIP for AXI Protocol☆176May 24, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RISC-V Online Help☆36Aug 13, 2025Updated 9 months ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆129May 14, 2022Updated 4 years ago
- I2C slave Verilog Design and TestBench☆27May 9, 2019Updated 7 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆28Oct 31, 2021Updated 4 years ago
- Verification IP for APB protocol☆77Dec 18, 2020Updated 5 years ago
- ☆16May 6, 2026Updated 3 weeks ago
- ☆47Jun 4, 2023Updated 2 years ago