ShashankSirohiya / 100DaysOfRtlView external linksLinks
I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
☆26Jul 23, 2023Updated 2 years ago
Alternatives and similar repositories for 100DaysOfRtl
Users that are interested in 100DaysOfRtl are comparing it to the libraries listed below
Sorting:
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Jun 4, 2024Updated last year
- ☆10Oct 16, 2023Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆19Oct 18, 2023Updated 2 years ago
- ☆116Dec 24, 2023Updated 2 years ago
- ☆44Jul 20, 2023Updated 2 years ago
- ☆18Feb 26, 2024Updated last year
- ☆23Feb 10, 2024Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆109Jul 9, 2023Updated 2 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆20Aug 5, 2023Updated 2 years ago
- DMA Project using Verilog HDL☆13Dec 26, 2019Updated 6 years ago
- ☆16Mar 27, 2024Updated last year
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.