Alternatives and similar repositories for 6T-SRAM_cell_design

Users that are interested in 6T-SRAM_cell_design are comparing it to the libraries listed below

• bmurmann / ADC-survey
  ADC Performance Survey (ISSCC & VLSI Circuit Symposium)
  ☆208Updated 3 weeks ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆70Updated last year
• imc-trading / svlangserver
  ☆117Updated last year
• ColsonZhang / VerilogA-Wave-Generator
  The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…
  ☆54Updated 3 years ago
• sandarm-1 / Gm_over_Id_methodology
  Gm over Id methodology
  ☆26Updated 3 years ago
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆90Updated 6 years ago
• truecrab / VSCode_Extension_Verilog
  VSCode extension for enhancing verilog
  ☆25Updated last year
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆51Updated 2 years ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆181Updated 5 years ago
• The-OpenROAD-Project / asap7
  ☆179Updated 5 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆234Updated 11 months ago
• pkuzjx / EDA-wiki
  EDA wiki
  ☆131Updated 4 months ago
• bmurmann / Book-on-gm-ID-design
  Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"
  ☆157Updated last week
• RongyeL / EasyAXI
  ☆53Updated this week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆220Updated 2 weeks ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆96Updated last month
• n-kremeris / vivado-scripted-flow
  ☆13Updated 4 years ago
• thomasrussellmurphy / istyle-verilog-formatter
  Open source implementation of a Verilog formatter
  ☆180Updated 3 years ago
• ncsu-eda / FreePDK3
  ☆162Updated 3 years ago
• yportne13 / SpinalResNet
  AdderNet ResNet20 for cifar10 written in SpinalHDL
  ☆35Updated 4 years ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆118Updated 12 years ago
• VardhanSuroshi / Memory-Design-And-Testing
  The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso
  ☆34Updated last year
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 8 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆139Updated last year
• viktor-nikolov / Zynq-XADC-DMA-lwIP
  Tutorial for analog input digitalization by the Xilinx Zynq XADC utilizing the DMA and data streaming to a PC over the network.
  ☆15Updated 8 months ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆54Updated 6 years ago
• mperov / fixSegfaultVCS
  There is segmentation fault of VCS which should be fixed.
  ☆35Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆89Updated 3 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆78Updated 4 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆138Updated last year