This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
☆21Apr 20, 2019Updated 7 years ago
Alternatives and similar repositories for Modeling-of-4-bit-Flash-ADC-and-4-bit-DAC
Users that are interested in Modeling-of-4-bit-Flash-ADC-and-4-bit-DAC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆17Sep 12, 2023Updated 2 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆40Apr 7, 2019Updated 7 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆26May 2, 2025Updated last year
- 9-bit SAR in skywater 130 nm☆18Jan 15, 2025Updated last year
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆94Jun 12, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Schematic, Layout Design & Simulation in 180nm Technology☆23Nov 21, 2020Updated 5 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆91Mar 19, 2026Updated 4 months ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆16Mar 17, 2019Updated 7 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆32Feb 21, 2019Updated 7 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆29Jan 2, 2021Updated 5 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆226Nov 13, 2024Updated last year
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆15Jan 2, 2021Updated 5 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆64Mar 21, 2024Updated 2 years ago
- Advanced integrated circuits 2023☆35Feb 25, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆20May 28, 2021Updated 5 years ago
- Solve one design problem each day for a month☆55Feb 3, 2023Updated 3 years ago
- nn2FPGA converts ONNX models into FPGA dataflow accelerators with seamless ONNX Runtime integration.☆21Jul 21, 2026Updated last week
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆57Dec 16, 2025Updated 7 months ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆223Oct 6, 2025Updated 9 months ago
- VerilogAI – A specialized chatbot for Verilog. Supports code generation, debugging, and explanation with custom prompt engineering and AP…☆18Apr 26, 2026Updated 3 months ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆41Jun 10, 2021Updated 5 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆10Sep 7, 2023Updated 2 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- Ten Thousand Failures Blog☆12Jul 22, 2014Updated 12 years ago
- ☆13Jan 25, 2023Updated 3 years ago
- Gm over Id methodology☆42Jun 8, 2022Updated 4 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆21Dec 15, 2020Updated 5 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆36Jan 23, 2024Updated 2 years ago
- ☆16Jul 14, 2024Updated 2 years ago
- Projects with Software Defined Radio (SDR) for Computer Networks Class☆16Dec 1, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- Getting started with RISC-V☆14Jun 4, 2023Updated 3 years ago
- PLL Designs on Skywater 130nm MPW☆25Dec 3, 2023Updated 2 years ago
- IHP Open source SG13G2 Tape Out on April 2025 [Testfield T586]☆17Apr 27, 2026Updated 3 months ago
- Vitis-AI 1.3 TensorFlow2 flow with a custom CNN model, targeted ZCU102 evaluation board.☆15Apr 6, 2021Updated 5 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆63Mar 13, 2025Updated last year
- Testfield: T593☆15Apr 27, 2026Updated 3 months ago