This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A comparison is done between several topologies, showing the ENOB, SNR, & SFDR achieved in each case.
☆13Jul 8, 2019Updated 7 years ago
Alternatives and similar repositories for Analog-Design-of-Bootstrapped-Switch
Users that are interested in Analog-Design-of-Bootstrapped-Switch are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆17Sep 12, 2023Updated 2 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆21Apr 20, 2019Updated 7 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆26May 2, 2025Updated last year
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆44Mar 2, 2022Updated 4 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆15Jan 2, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- 9-bit SAR in skywater 130 nm☆18Jan 15, 2025Updated last year
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆226Nov 13, 2024Updated last year
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆40Apr 7, 2019Updated 7 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆32Feb 21, 2019Updated 7 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆29Jan 2, 2021Updated 5 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆94Jun 12, 2023Updated 3 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆16Mar 17, 2019Updated 7 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆29Jun 4, 2024Updated 2 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆91Mar 19, 2026Updated 4 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆13Aug 26, 2024Updated last year
- Python package for design and simulation of RF phase-locked loops☆15Apr 23, 2022Updated 4 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆41Jun 10, 2021Updated 5 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- Motion Estimation implementation by using Verilog HDL☆13Jun 17, 2024Updated 2 years ago
- MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System☆32Mar 21, 2017Updated 9 years ago
- Advanced integrated circuits 2023☆35Feb 25, 2024Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆44Jun 13, 2023Updated 3 years ago
- ☆13Jan 25, 2023Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆12Dec 11, 2023Updated 2 years ago
- ☆14Oct 22, 2023Updated 2 years ago
- repository for a bandgap voltage reference in SKY130 technology☆44Jan 20, 2023Updated 3 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆36Jan 23, 2024Updated 2 years ago
- ☆12Oct 29, 2022Updated 3 years ago
- A 10bit SAR ADC in Sky130☆40Dec 4, 2022Updated 3 years ago
- Matlab implementation of polar codes for a BEC☆11Dec 1, 2017Updated 8 years ago
- Design of LDO using open source SKY130PDK☆17Aug 24, 2024Updated last year
- ☆16Jul 14, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆74Apr 9, 2018Updated 8 years ago
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆16Feb 22, 2026Updated 5 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆61Updated this week
- the demo codes for New Concept C Language☆13May 14, 2014Updated 12 years ago
- FYP: An Application of 24GHz RADAR for Contactless Heart-Rate Monitoring☆14Jun 1, 2021Updated 5 years ago
- Distributed variational Bayesian algorithms over sensor networks☆12Jun 30, 2017Updated 9 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago