muhammadaldacher / Analog-Design-of-Bootstrapped-SwitchLinks
This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A comparison is done between several topologies, showing the ENOB, SNR, & SFDR achieved in each case.
☆12Updated 6 years ago
Alternatives and similar repositories for Analog-Design-of-Bootstrapped-Switch
Users that are interested in Analog-Design-of-Bootstrapped-Switch are comparing it to the libraries listed below
Sorting:
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆76Updated 2 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆181Updated 11 months ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆35Updated 3 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆35Updated 6 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆163Updated 3 weeks ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆12Updated 6 years ago
- Advanced integrated circuits 2023☆32Updated last year
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆15Updated 2 years ago
- Python library for SerDes modelling☆73Updated last year
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆102Updated 6 months ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆167Updated 2 months ago
- ☆106Updated 3 weeks ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆11Updated 3 years ago
- Solve one design problem each day for a month☆48Updated 2 years ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆61Updated this week
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆80Updated 3 years ago
- A python3 gm/ID starter kit☆54Updated 2 months ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 8 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆89Updated last year
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆26Updated last year
- Read Spectre PSF files☆69Updated 2 months ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆48Updated 5 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Updated 4 years ago
- MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System☆30Updated 8 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆26Updated 4 years ago
- ☆83Updated 9 months ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆32Updated 4 years ago
- repository for a bandgap voltage reference in SKY130 technology☆40Updated 2 years ago
- ☆86Updated last month
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆50Updated last month