muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOSView on GitHub
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
☆29Feb 21, 2019Updated 7 years ago
Alternatives and similar repositories for Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
Users that are interested in Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆42Mar 2, 2022Updated 4 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆82Jun 12, 2023Updated 2 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆27Jan 2, 2021Updated 5 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆24May 2, 2025Updated 10 months ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆14Mar 17, 2019Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆198Nov 13, 2024Updated last year
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆12Jul 8, 2019Updated 6 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆18Apr 20, 2019Updated 6 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆37Apr 7, 2019Updated 6 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆14Jul 22, 2020Updated 5 years ago
- Schematic, Layout Design & Simulation in 180nm Technology☆22Nov 21, 2020Updated 5 years ago
- Advanced integrated circuits 2023☆32Feb 25, 2024Updated 2 years ago
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Nov 13, 2020Updated 5 years ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆25May 30, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆11Apr 25, 2020Updated 5 years ago
- 8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving…☆15Jul 21, 2022Updated 3 years ago
- A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file☆13Sep 3, 2018Updated 7 years ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆19Nov 29, 2020Updated 5 years ago
- Open Analog Design Environment☆25May 19, 2023Updated 2 years ago
- ☆15Jun 22, 2023Updated 2 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆87Mar 19, 2026Updated last week
- 9-bit SAR in skywater 130 nm☆17Jan 15, 2025Updated last year
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆74Updated this week
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A 10bit SAR ADC in Sky130☆34Dec 4, 2022Updated 3 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆40Jun 10, 2021Updated 4 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆30Jan 23, 2024Updated 2 years ago
- Open Source PHY v2☆33Apr 25, 2024Updated last year
- Repository of Matlab tools for analysis of wireline signal integrity and transceiver simulation☆14Apr 25, 2020Updated 5 years ago
- repository for a bandgap voltage reference in SKY130 technology☆42Jan 20, 2023Updated 3 years ago
- An EDA tool for automatic device sizing using Gm/Id method.☆15Jan 10, 2026Updated 2 months ago
- skywater 130nm pdk☆44Mar 16, 2026Updated 2 weeks ago
- LibreSilicon's Standard Cell Library Generator☆22Oct 30, 2025Updated 5 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- awesome-Analog-IC-Design-Automation☆48Apr 19, 2023Updated 2 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆14Dec 27, 2020Updated 5 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Mar 11, 2023Updated 3 years ago
- ☆41Feb 28, 2022Updated 4 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Jun 4, 2024Updated last year
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆25May 13, 2023Updated 2 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆20Dec 15, 2020Updated 5 years ago