muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOSView on GitHub
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
☆34Feb 21, 2019Updated 7 years ago
Alternatives and similar repositories for Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
Users that are interested in Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆45Mar 2, 2022Updated 4 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆31Jan 2, 2021Updated 5 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆95Jun 12, 2023Updated 3 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆26May 2, 2025Updated last year
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆17Mar 17, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆234Nov 13, 2024Updated last year
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆17Sep 12, 2023Updated 2 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆40Apr 7, 2019Updated 7 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆21Apr 20, 2019Updated 7 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆16Jul 22, 2020Updated 6 years ago
- Schematic, Layout Design & Simulation in 180nm Technology☆23Nov 21, 2020Updated 5 years ago
- VSD workshop - Phase Locked Loop(PLL) IC Design☆17Aug 4, 2021Updated 5 years ago
- Advanced integrated circuits 2023☆36Feb 25, 2024Updated 2 years ago
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Nov 13, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆11Apr 25, 2020Updated 6 years ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆19Nov 29, 2020Updated 5 years ago
- 8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving…☆16Jul 21, 2022Updated 4 years ago
- Open Analog Design Environment☆26May 19, 2023Updated 3 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆96Mar 19, 2026Updated 5 months ago
- 9-bit SAR in skywater 130 nm☆18Jan 15, 2025Updated last year
- A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file☆15Sep 3, 2018Updated 8 years ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆32May 30, 2024Updated 2 years ago
- Open Source PHY v2☆40Apr 25, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- An EDA tool for automatic device sizing using Gm/Id method.☆18Jan 10, 2026Updated 7 months ago
- repository for a bandgap voltage reference in SKY130 technology☆45Jan 20, 2023Updated 3 years ago
- Repository of Matlab tools for analysis of wireline signal integrity and transceiver simulation☆14Apr 25, 2020Updated 6 years ago
- LibreSilicon's Standard Cell Library Generator☆22Aug 22, 2026Updated 2 weeks ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆82Updated this week
- Basic Simulink Blocks for modeling CDRs and PLLs☆17Apr 25, 2020Updated 6 years ago
- A Python and SKILL Framework for Cadence Virtuoso☆57Dec 13, 2025Updated 8 months ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆32Jun 4, 2024Updated 2 years ago
- ☆42Feb 28, 2022Updated 4 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- A 10bit SAR ADC in Sky130☆41Dec 4, 2022Updated 3 years ago
- a curated "awesome list" of open-source hardware Intellectual Property (IP) blocks designed specifically for the SkyWater 130nm (SKY130) …☆30Apr 18, 2026Updated 4 months ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆28Mar 11, 2023Updated 3 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆21Dec 15, 2020Updated 5 years ago
- Model SAR ADC with python!☆22Jul 8, 2022Updated 4 years ago