muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
☆20Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆28Updated 2 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆21Updated 3 years ago
- cdsAsync: An Asynchronous VLSI Toolset & Schematic Library☆25Updated 5 years ago
- A 10bit SAR ADC in Sky130☆19Updated last year
- submission repository for efabless mpw6 shuttle☆30Updated 9 months ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆26Updated 2 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆13Updated 5 years ago
- ☆16Updated 2 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆26Updated 3 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆18Updated 3 years ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆14Updated 5 months ago
- ☆20Updated 2 years ago
- repository for a bandgap voltage reference in SKY130 technology☆34Updated last year
- PLL Designs on Skywater 130nm MPW☆20Updated 11 months ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 3 years ago
- A simple MOSFET model with only 5-DC-parameters for circuit simulation☆38Updated 4 months ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 3 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆28Updated last year
- Open Analog Design Environment☆22Updated last year
- LibreSilicon's Standard Cell Library Generator☆17Updated 6 months ago
- This repository is for (pre-)release versions of the Revolution EDA.☆35Updated this week
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆8Updated 8 months ago
- Analog and power building blocks for sky130 pdk☆20Updated 3 years ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆55Updated last month
- Digital Standard Cells based SAR ADC☆11Updated 3 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- A tiny Python package to parse spice raw data files.☆43Updated last year
- Skywater 130nm Klayout Device Generators PDK☆29Updated 3 months ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆21Updated 5 months ago
- Open Source PHY v2☆25Updated 6 months ago