muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOSView on GitHub
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
☆35Feb 21, 2019Updated 7 years ago
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