muhammadaldacher / Analog-design-of-4-bit-current-steering-DACsLinks
This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using high-swing cascode current mirror structures for the current source arrays.
☆21Updated 8 months ago
Alternatives and similar repositories for Analog-design-of-4-bit-current-steering-DACs
Users that are interested in Analog-design-of-4-bit-current-steering-DACs are comparing it to the libraries listed below
Sorting:
- ☆13Updated 3 years ago
- ☆17Updated 3 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆20Updated 5 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆38Updated 3 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆25Updated 5 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆26Updated 6 years ago
- ☆20Updated 4 years ago
- ☆42Updated 3 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Updated 3 weeks ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆38Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆24Updated 4 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 4 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆39Updated 4 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆14Updated 5 years ago
- PLL Designs on Skywater 130nm MPW☆22Updated 2 years ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆64Updated 4 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 4 years ago
- repository for a bandgap voltage reference in SKY130 technology☆41Updated 2 years ago
- Completed LDO Design for Skywaters 130nm☆18Updated 2 years ago
- ☆14Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- A 10bit SAR ADC in Sky130☆27Updated 3 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆22Updated 2 years ago
- Open source process design kit for 28nm open process☆72Updated last year
- Analog and power building blocks for sky130 pdk☆22Updated 4 years ago
- This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Proce…☆29Updated 2 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆67Updated last month
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago