muhammadaldacher / RF-design-of-2.4-GHz-LNALinks
This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.
☆12Updated 6 years ago
Alternatives and similar repositories for RF-design-of-2.4-GHz-LNA
Users that are interested in RF-design-of-2.4-GHz-LNA are comparing it to the libraries listed below
Sorting:
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆76Updated 2 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Updated 4 years ago
- ☆43Updated 3 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆181Updated 11 months ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆35Updated 6 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆89Updated last year
- ☆13Updated this week
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆50Updated 4 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated 2 years ago
- ☆83Updated 9 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆35Updated 3 years ago
- Solve one design problem each day for a month☆48Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆26Updated 4 years ago
- repository for a bandgap voltage reference in SKY130 technology☆40Updated 2 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆80Updated 3 years ago
- ☆13Updated last year
- ☆106Updated 3 weeks ago
- Design Verification Engineer interview preparation guide.☆38Updated 3 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆43Updated 3 years ago
- ☆17Updated 3 years ago
- A 10bit SAR ADC in Sky130☆25Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆33Updated 2 years ago
- PLL Designs on Skywater 130nm MPW☆21Updated last year
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆22Updated last year
- ☆17Updated 2 years ago