muhammadaldacher / RF-design-of-2.4-GHz-LNALinks
This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.
☆14Updated 6 years ago
Alternatives and similar repositories for RF-design-of-2.4-GHz-LNA
Users that are interested in RF-design-of-2.4-GHz-LNA are comparing it to the libraries listed below
Sorting:
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆72Updated 2 years ago
- ☆42Updated 3 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Updated 4 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- repository for a bandgap voltage reference in SKY130 technology☆39Updated 2 years ago
- ☆13Updated last year
- ☆84Updated 7 months ago
- ☆12Updated 4 months ago
- PLL Designs on Skywater 130nm MPW☆21Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆48Updated 4 years ago
- ☆99Updated last week
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆15Updated 5 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- ☆41Updated last year
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆33Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆65Updated 2 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆40Updated 3 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated last year
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆15Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆16Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆75Updated last year
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆24Updated last year
- Blocks & Bots: An Open Chip Playground augmented with LLMs. Please check: https://sscs.ieee.org/technical-committees/tc-ose/sscs-pico-des…☆66Updated last week
- Design of miller compensated 2 stage opamp using open source SKY130PDK☆12Updated 2 months ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆74Updated 3 years ago
- ☆16Updated 2 years ago
- Home of the open-source EDA course.☆43Updated 2 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆74Updated 4 years ago
- Design Verification Engineer interview preparation guide.☆33Updated last month