akdimitri / RRAM_COMPILERLinks
This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College London
☆77Updated 3 years ago
Alternatives and similar repositories for RRAM_COMPILER
Users that are interested in RRAM_COMPILER are comparing it to the libraries listed below
Sorting:
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆75Updated 2 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆25Updated 4 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆30Updated 2 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Updated 3 years ago
- Architecture for RRAM multilevel programming☆17Updated 7 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Updated 4 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆76Updated 10 months ago
- A RRAM addon for the NCSU FreePDK 45nm☆24Updated 4 years ago
- sram/rram/mram.. compiler☆44Updated 2 years ago
- Template for project1 TPU☆21Updated 4 years ago
- Central repository for all NeuroSim versions. Each version is uploaded in a separate branch. Updates to the versions will be reflected he…☆100Updated this week
- a Computing In Memory emULATOR framework☆14Updated last year
- Physical memristor/RRAM/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices sett…☆46Updated 6 years ago
- A scalable FeFET compact model☆18Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆75Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆78Updated last month
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Updated 6 years ago
- Verilog and Python drivers and APIs for Neurram 48-core chip☆44Updated 3 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆200Updated 5 years ago
- [TVLSI 2025] ACiM Inference Simulation Framework in "ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits"☆25Updated 4 months ago
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆113Updated 2 months ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Updated 6 years ago
- ☆40Updated 6 years ago
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- This is a tutorial on standard digital design flow☆83Updated 4 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆72Updated 5 months ago
- ☆20Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆36Updated 3 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆72Updated 5 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago