akdimitri / RRAM_COMPILERLinks
This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College London
☆74Updated 3 years ago
Alternatives and similar repositories for RRAM_COMPILER
Users that are interested in RRAM_COMPILER are comparing it to the libraries listed below
Sorting:
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆74Updated 2 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆24Updated 4 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆15Updated 2 years ago
- Architecture for RRAM multilevel programming☆17Updated 7 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆76Updated 8 months ago
- a Computing In Memory emULATOR framework☆14Updated last year
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆66Updated 2 weeks ago
- A Spiking Neuron Network Project in Verilog Implementation☆25Updated 7 years ago
- [TVLSI 2025] ACiM Inference Simulation Framework in "ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits"☆23Updated 2 months ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Updated 6 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Updated 4 years ago
- ☆37Updated 6 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆24Updated 3 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆191Updated 5 years ago
- ☆14Updated 3 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆29Updated 2 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆107Updated 5 years ago
- Physical memristor/RRAM/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices sett…☆46Updated 6 years ago
- Template for project1 TPU☆19Updated 4 years ago
- Spiking Neural Network Accelerator☆15Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆60Updated 8 months ago
- sram/rram/mram.. compiler☆42Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆28Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆74Updated last year
- ☆44Updated last year