☆119Dec 24, 2023Updated 2 years ago
Alternatives and similar repositories for 100-Days-of-RTL
Users that are interested in 100-Days-of-RTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Apr 18, 2026Updated 2 months ago
- ☆45Jul 20, 2023Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆38Jul 23, 2023Updated 2 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆20Aug 5, 2023Updated 2 years ago
- ☆18Jun 12, 2023Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆22May 25, 2023Updated 3 years ago
- 100 Days of RTL☆418Aug 15, 2024Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆120Jul 9, 2023Updated 2 years ago
- ☆10Oct 16, 2023Updated 2 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- ☆19Feb 26, 2024Updated 2 years ago
- Trying to get a new skill☆38Dec 31, 2024Updated last year
- ☆17Jan 13, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆91Mar 19, 2026Updated 3 months ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Jan 2, 2021Updated 5 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆33Sep 16, 2023Updated 2 years ago
- This repository contains solutions to the practice problems available on the HDLBits platform, which cover a wide range of topics in Digi…☆13Apr 24, 2023Updated 3 years ago
- Open Source VLSI Tools☆32Feb 6, 2021Updated 5 years ago
- Verilog Fundamentals Explained for Beginners and Professionals☆20Jan 15, 2023Updated 3 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆27Aug 11, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆16Aug 13, 2023Updated 2 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆40Nov 6, 2022Updated 3 years ago
- This repository contains source code for past labs and projects involving FPGA and Verilog based designs☆121Oct 2, 2019Updated 6 years ago
- Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functi…☆29Nov 21, 2020Updated 5 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- Hardware Implementation of low-bit rate Codec, Codec2 in Verilog RTL on Cyclone IV FPGA.☆15Mar 29, 2020Updated 6 years ago
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆16Oct 18, 2014Updated 11 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- 30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…☆67Sep 30, 2023Updated 2 years ago
- UART implementation using verilog☆38Feb 14, 2023Updated 3 years ago
- ☆25Nov 4, 2023Updated 2 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆114Jul 2, 2023Updated 2 years ago
- VIP for AXI Protocol☆179May 24, 2022Updated 4 years ago
- ☆18Jun 2, 2025Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆81Oct 7, 2022Updated 3 years ago