☆119Dec 24, 2023Updated 2 years ago
Alternatives and similar repositories for 100-Days-of-RTL
Users that are interested in 100-Days-of-RTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆45Jul 20, 2023Updated 3 years ago
- ☆11Apr 18, 2026Updated 3 months ago
- ☆18Jun 12, 2023Updated 3 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆21Aug 5, 2023Updated 2 years ago
- ☆10Oct 16, 2023Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆22May 25, 2023Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆123Jul 9, 2023Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆39Jul 23, 2023Updated 3 years ago
- 100 Days of RTL☆423Aug 15, 2024Updated last year
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- ☆19Feb 26, 2024Updated 2 years ago
- ☆17Jan 13, 2024Updated 2 years ago
- Trying to get a new skill☆38Dec 31, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆91Mar 19, 2026Updated 4 months ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆33Sep 16, 2023Updated 2 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆15Jan 2, 2021Updated 5 years ago
- Verilog Fundamentals Explained for Beginners and Professionals☆20Jan 15, 2023Updated 3 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆17Aug 13, 2023Updated 2 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- Verilog/SystemVerilog Guide☆90Jan 4, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆27Aug 11, 2022Updated 3 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- ☆49Apr 7, 2024Updated 2 years ago
- Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functi…☆30Nov 21, 2020Updated 5 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆40Nov 6, 2022Updated 3 years ago
- Open Source VLSI Tools☆33Feb 6, 2021Updated 5 years ago
- This repository contains source code for past labs and projects involving FPGA and Verilog based designs☆122Oct 2, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆17Oct 18, 2014Updated 11 years ago
- ☆25Nov 4, 2023Updated 2 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆82Oct 7, 2022Updated 3 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆115Jul 2, 2023Updated 3 years ago
- VIP for AXI Protocol☆182May 24, 2022Updated 4 years ago
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆50Jul 18, 2020Updated 6 years ago
- All the projects and assignments done as part of VLSI course.☆20Sep 23, 2020Updated 5 years ago