Alternatives and similar repositories for 100-Days-of-RTL

Users that are interested in 100-Days-of-RTL are comparing it to the libraries listed below

• karribharathi / 100-Days-of-RTL
  ☆16Updated last year
• Prajwal-ECE / RTL-Coding
  ☆9Updated 2 years ago
• KOTHAVANI / 100-Days-of-RTL-code
  ☆41Updated last year
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆76Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆30Updated 5 years ago
• ashok-g-r / 100-Days-of-RTL
  ☆16Updated last year
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆15Updated last year
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆149Updated 8 months ago
• Abhishek-Sharma182005 / 108-RTL-Projects
  Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…
  ☆13Updated 3 months ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆58Updated 2 years ago
• Artityagi123456789 / 100DaysofRTL
  ☆16Updated last year
• shubhi704 / APB-Protocol
  ☆42Updated 3 years ago
• Prananya123 / RTL-Coding
  ☆22Updated last year
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆17Updated last year
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated last year
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆32Updated last year
• ChinnuReddySeelam / 100DaysRTL_Part1_HDL
  ☆10Updated last year
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆102Updated 11 years ago
• Vivek-Dave / UVM_TestBench_For_Single_Port_RAM
  A complete UVM TB for verification of single port 64KB RAM
  ☆15Updated 4 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆88Updated last year
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆134Updated 2 years ago
• ItzzInfinity / 100-days-of-RTL
  Trying to get a new skill
  ☆23Updated 4 months ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆110Updated 3 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆42Updated 6 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆122Updated 4 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆57Updated last year
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆120Updated last year
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆17Updated last year
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆71Updated 2 years ago