This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
☆42Apr 7, 2019Updated 7 years ago
Alternatives and similar repositories for Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
Users that are interested in Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆23Apr 20, 2019Updated 7 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆18Sep 12, 2023Updated 3 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆48Mar 2, 2022Updated 4 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆26May 2, 2025Updated last year
- 9-bit SAR in skywater 130 nm☆21Jan 15, 2025Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- This project shows the design process of the main blocks of a typical RX frontend system.☆32Jan 2, 2021Updated 5 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆247Nov 13, 2024Updated last year
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆13Jul 8, 2019Updated 7 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆99Jun 12, 2023Updated 3 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆18Mar 17, 2019Updated 7 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆35Feb 21, 2019Updated 7 years ago
- Solve one design problem each day for a month☆56Feb 3, 2023Updated 3 years ago
- Fundamental analog circuit designs to kick start and embark the journey in the world of IC design.☆34Aug 31, 2023Updated 3 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆16Jan 2, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆32Jun 4, 2024Updated 2 years ago
- Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC☆29Jun 12, 2018Updated 8 years ago
- Low Power VLSI Design Concepts & Interview Questions for Top Semiconductor MNCs☆12Jan 12, 2023Updated 3 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆21Dec 15, 2020Updated 5 years ago
- ☆15Dec 2, 2021Updated 4 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆68Mar 13, 2025Updated last year
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆57Dec 16, 2025Updated 10 months ago
- ☆42Feb 28, 2022Updated 4 years ago
- We are designing a CP-PLL. The following link provides resources about PLL design.☆13Sep 20, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆29Jun 29, 2024Updated 2 years ago
- Simulink model for noise shaping SAR ADC☆14Mar 17, 2020Updated 6 years ago
- An open-source Ternary Content Addressable Memory (TCAM) compiler.☆39Jul 19, 2024Updated 2 years ago
- VerilogAI – A specialized chatbot for Verilog. Supports code generation, debugging, and explanation with custom prompt engineering and AP…☆19Apr 26, 2026Updated 6 months ago
- nn2FPGA converts ONNX models into FPGA dataflow accelerators with seamless ONNX Runtime integration.☆25Updated this week
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆51Mar 22, 2019Updated 7 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆258Oct 6, 2025Updated last year
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆34May 30, 2024Updated 2 years ago
- A Python library for communicating with SCPI devices and a helper library for communicating with the Keysight's Smart Bench Essentials☆12Feb 2, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆126Jul 31, 2021Updated 5 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- This project discusses the design procedure of a Low Dropout Voltage Regulator (LDO) circuit.☆33Feb 28, 2024Updated 2 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- ☆14Aug 24, 2026Updated 2 months ago
- Skywaters 130nm Klayout PDK☆37Jan 29, 2025Updated last year
- IHP Open source SG13G2 Tape Out on May 2025 [Testfield T588]☆15Apr 27, 2026Updated 6 months ago
Are these results useful?