Danishazmi29 / Verilog-Code-of-Synchronus-FIFO-Design-with-verilog-test-codeLinks
A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. There are many other use of FIFO also. FIFO uses a dual port memory and there will be two pointers to point read and write addresses. Here is a generalized block diagram of FIFO.
☆15Updated 7 years ago
Alternatives and similar repositories for Verilog-Code-of-Synchronus-FIFO-Design-with-verilog-test-code
Users that are interested in Verilog-Code-of-Synchronus-FIFO-Design-with-verilog-test-code are comparing it to the libraries listed below
Sorting:
- Asynchronous fifo in verilog☆35Updated 9 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆19Updated last month
- ☆19Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆29Updated last year
- ☆43Updated 4 years ago
- Sample UVM code for axi ram dut☆34Updated 3 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆48Updated 4 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- System Verilog using Functional Verification☆12Updated last year
- Verification IP for APB protocol☆66Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆63Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆33Updated 2 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆56Updated last year
- Verilog Project☆13Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- AXI Interconnect☆50Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Structured UVM Course☆43Updated last year
- Architectural design of data router in verilog☆31Updated 5 years ago
- General purpose IO port with AXI4-Lite interface☆10Updated 4 months ago
- APB to I2C☆41Updated 10 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 3 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆52Updated 4 years ago