J-Core J2/J32 5 stage pipeline CPU core
☆61Nov 24, 2020Updated 5 years ago
Alternatives and similar repositories for jcore-cpu
Users that are interested in jcore-cpu are comparing it to the libraries listed below
Sorting:
- J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.☆28Nov 24, 2020Updated 5 years ago
- J-core SOC for ice40 FPGA☆20Dec 8, 2019Updated 6 years ago
- Heritage of Sun Microsystems☆10Feb 11, 2021Updated 5 years ago
- LEON2 SPARC CPU IP core LGPL by Gaisler Research☆20Apr 9, 2013Updated 12 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated last year
- GCC port for OpenRISC 1000☆26Mar 29, 2025Updated 10 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Feb 3, 2026Updated 3 weeks ago
- Baseband Receiver IP for GPS like DSSS signals☆40May 19, 2020Updated 5 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- A pipelined RISC-V processor☆63Dec 1, 2023Updated 2 years ago
- Interface definitions for VHDL-2019.☆34Jan 12, 2026Updated last month
- FreeBSD src tree☆18Oct 12, 2020Updated 5 years ago
- A computer (FPGA SoC) based on the MRISC32-A1 CPU☆53Sep 2, 2023Updated 2 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- A tiny Open POWER ISA softcore written in VHDL 2008☆711Feb 4, 2026Updated 3 weeks ago
- Homebrew walking simulator for Nintendo DS☆12Dec 3, 2022Updated 3 years ago
- Gate array reverse engineering☆29Dec 28, 2025Updated last month
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆224Feb 19, 2026Updated last week
- adding Irix (and, to a lesser extend, Solaris) userland emulation to QEMU☆25Jul 17, 2019Updated 6 years ago
- Sparc emulator☆11May 19, 2018Updated 7 years ago
- vhdl related contents☆11Apr 27, 2020Updated 5 years ago
- A profiling library for the Sega Dreamcast☆12May 15, 2025Updated 9 months ago
- Nebulous for Dreamcast, with special thanks to Comby Laurent, Ian Micheal and LemonHaze☆10Jun 22, 2022Updated 3 years ago
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 5 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- Amos interpreter under development, most commands are support, some extensions are supported.☆10Sep 27, 2022Updated 3 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- Firmware for Xilinx Platform Cable 1 USB Jtag adapter☆10Jul 24, 2016Updated 9 years ago
- Snake on the Dreamcast memory card peripheral device☆14Jan 13, 2023Updated 3 years ago
- Network protocol libraries for VHDL test benches☆13Jan 11, 2026Updated last month
- Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…☆73Jan 1, 2026Updated last month
- Verilog re-implementation of the famous CAPCOM arcade game☆29Jan 25, 2019Updated 7 years ago
- VHDL related news.☆27Updated this week
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- FX68K 68000 cycle accurate SystemVerilog core☆160Jun 1, 2021Updated 4 years ago
- Dreamcast optimized version for use with your indie game☆10Oct 26, 2024Updated last year
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆14Feb 22, 2019Updated 7 years ago