j-core / jcore-cpuLinks
J-Core J2/J32 5 stage pipeline CPU core
☆53Updated 4 years ago
Alternatives and similar repositories for jcore-cpu
Users that are interested in jcore-cpu are comparing it to the libraries listed below
Sorting:
- 5-stage RISC-V CPU, originally developed for RISCBoy☆32Updated 2 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆63Updated 4 months ago
- Verilog re-implementation of the famous CAPCOM arcade game☆29Updated 6 years ago
- J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.☆25Updated 4 years ago
- OpenGL 1.x implementation for FPGAs☆100Updated this week
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆45Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆46Updated 7 months ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆45Updated last month
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 2 weeks ago
- A very simple RISC-V ISA emulator.☆38Updated 4 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated 2 years ago
- 16 bit RISC-V proof of concept☆24Updated last year
- 65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface☆73Updated 2 years ago
- A computer (FPGA SoC) based on the MRISC32-A1 CPU☆55Updated 2 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆49Updated 4 months ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆33Updated 8 years ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- Exploring gate level simulation☆58Updated 5 months ago
- Homebrew game for homebrew FPGA game console☆50Updated 4 years ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆16Updated 2 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- The Chameleon96™ board, based on Intel® Cyclone V SoC FPGA☆15Updated last year
- Design digital circuits in C. Simulate really fast with a regular compiler.☆174Updated 2 years ago
- Compact FPGA game console☆166Updated last year
- IBM PC Compatible SoC for a commercially available FPGA board☆72Updated 8 years ago
- Website documenting a hardware project from the 1990s.☆76Updated 2 years ago
- Doom classic port to lightweight RISC‑V☆97Updated 3 years ago
- This is a higan/Verilator co-simulation example/framework☆51Updated 7 years ago
- Designing Video Game Hardware in Verilog☆27Updated 5 years ago
- A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano☆40Updated 5 years ago