j-core / jcore-cpuLinks
J-Core J2/J32 5 stage pipeline CPU core
☆53Updated 4 years ago
Alternatives and similar repositories for jcore-cpu
Users that are interested in jcore-cpu are comparing it to the libraries listed below
Sorting:
- J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.☆24Updated 4 years ago
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆44Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 4 months ago
- Verilog re-implementation of the famous CAPCOM arcade game☆29Updated 6 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated 3 weeks ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆41Updated last month
- A bit-serial CPU☆19Updated 5 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆58Updated this week
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆15Updated last year
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆47Updated last month
- ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts☆39Updated 4 years ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆32Updated 8 years ago
- HDMI core in Chisel HDL☆51Updated last year
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- 16 bit RISC-V proof of concept☆24Updated 9 months ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 3 weeks ago
- iCE40HX8K development board with SRAM and bus for fast ADC, DAC, IOs☆35Updated 7 months ago
- Exploring gate level simulation☆58Updated last month
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆44Updated 5 months ago
- Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)☆37Updated 3 years ago
- OpenGL 1.x implementation for FPGAs☆90Updated last week
- A very simple RISC-V ISA emulator.☆37Updated 4 years ago
- Documenting the Microchip (Atmel) ATF15xx CPLD fuse maps and programming algorithms☆57Updated last week
- VGA-compatible text mode functionality☆17Updated 5 years ago
- A design for TinyTapeout☆16Updated 2 years ago
- Iron: selectively turn RISC-V binaries into hardware☆23Updated 2 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆98Updated 2 years ago
- FPGA raycaster engine written in verilog☆11Updated 6 years ago