sylefeb / IronLinks
Iron: selectively turn RISC-V binaries into hardware
☆23Updated 2 years ago
Alternatives and similar repositories for Iron
Users that are interested in Iron are comparing it to the libraries listed below
Sorting:
- Exploring gate level simulation☆58Updated 6 months ago
- An FPGA reverse engineering and documentation project☆58Updated 2 weeks ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated last week
- Hot Reconfiguration Technology demo☆41Updated 3 years ago
- Experiments with Yosys cxxrtl backend☆50Updated 9 months ago
- Graphics demos☆112Updated last year
- Soft USB for LiteX☆50Updated last month
- A Full Hardware Real-Time Ray-Tracer☆109Updated 3 years ago
- RISC-V out-of-order core for education and research purposes☆76Updated this week
- A reimplementation of a tiny stack CPU☆85Updated last year
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM☆24Updated 3 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- Unofficial Yosys WebAssembly packages☆74Updated last week
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆32Updated last year
- Reusable Verilog 2005 components for FPGA designs☆48Updated 8 months ago
- J-Core J2/J32 5 stage pipeline CPU core☆54Updated 4 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆36Updated 2 years ago
- Tiny tips for Colorlight i5 FPGA board☆58Updated 4 years ago
- Open source Logic Analyzer based on LiteX SoC☆26Updated 7 months ago
- Example Verilog code for Ulx3s☆42Updated 3 years ago
- Finding the bacteria in rotting FPGA designs.☆14Updated 4 years ago
- User-friendly explanation of Yosys options☆112Updated 4 years ago
- Industry standard I/O for Amaranth HDL☆30Updated last year
- Playground for experimenting with and sharing short Amaranth programs on the web☆18Updated 2 weeks ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆62Updated 6 months ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆19Updated last year
- OpenGL 1.x implementation for FPGAs☆105Updated last week
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated 11 months ago