Alternatives and similar repositories for Iron

Users that are interested in Iron are comparing it to the libraries listed below

• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆40Updated 2 years ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆47Updated this week
• darklife / udarkrisc
  u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
  ☆15Updated last year
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 4 months ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated last month
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆71Updated this week
• olofk / qerv
  ☆16Updated 3 weeks ago
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆35Updated last year
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 3 weeks ago
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated 2 years ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆29Updated 9 months ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 5 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆52Updated 4 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 7 months ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆38Updated 5 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• grayresearch / s3ga
  S3GA: a simple scalable serial FPGA
  ☆10Updated 2 years ago
• mattvenn / vga_clock_pcb
  Open source hardware down to the chip level!
  ☆30Updated 3 years ago
• jevinskie / riscv-smol-linux-kernel
  Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM
  ☆24Updated 2 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆93Updated 8 months ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆60Updated last year
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 3 years ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆41Updated last month
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆43Updated 3 months ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆49Updated 3 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• jrmoserbaltimore / risc-v-cpu-asynchronous
  A RISC-V CPU implementation
  ☆13Updated 5 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 3 years ago