Alternatives and similar repositories for Iron

Users that are interested in Iron are comparing it to the libraries listed below

• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 5 months ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆40Updated 3 years ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆58Updated 2 weeks ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 3 weeks ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 8 months ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆72Updated this week
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 11 months ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆29Updated 11 months ago
• darklife / udarkrisc
  u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
  ☆16Updated 2 years ago
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• jevinskie / riscv-smol-linux-kernel
  Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM
  ☆24Updated 2 years ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆63Updated last week
• Mr-Bossman / KISC-V
  KISCV, a KISS principle riscv32i CPU
  ☆25Updated 8 months ago
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆17Updated 3 years ago
• gatecat / tinytapeout-fpga-test
  ☆13Updated 3 years ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆56Updated 5 months ago
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆111Updated last year
• olofk / qerv
  ☆18Updated 4 months ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆89Updated 2 weeks ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆86Updated 5 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆32Updated 2 years ago
• ToNi3141 / RasterIX
  OpenGL 1.x implementation for FPGAs
  ☆100Updated this week
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆39Updated 10 months ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 6 years ago
• hamsternz / lfsr_scramblers
  Experiments with self-synchronizing LFSR scramblers
  ☆15Updated 4 years ago
• amaranth-lang / playground
  Playground for experimenting with and sharing short Amaranth programs on the web
  ☆15Updated last month
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆54Updated 4 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆61Updated last year