sylefeb / Iron
Iron: selectively turn RISC-V binaries into hardware
☆23Updated last year
Alternatives and similar repositories for Iron:
Users that are interested in Iron are comparing it to the libraries listed below
- Hot Reconfiguration Technology demo☆39Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆48Updated 3 months ago
- Exploring gate level simulation☆56Updated this week
- ☆22Updated 3 years ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆14Updated last year
- An FPGA reverse engineering and documentation project☆43Updated last week
- Unofficial Yosys WebAssembly packages☆70Updated this week
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 2 weeks ago
- S3GA: a simple scalable serial FPGA☆10Updated 2 years ago
- PicoRV☆44Updated 5 years ago
- Soft USB for LiteX☆50Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆90Updated 7 months ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆29Updated 7 months ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆29Updated 2 weeks ago
- Industry standard I/O for Amaranth HDL☆28Updated 6 months ago
- A Just-In-Time Compiler for Verilog from VMware Research☆22Updated 4 years ago
- J-Core J2/J32 5 stage pipeline CPU core☆52Updated 4 years ago
- A design for TinyTapeout☆16Updated 2 years ago
- ☆15Updated 4 months ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- A pipelined RISC-V processor☆55Updated last year
- KISCV, a KISS principle riscv32i CPU☆21Updated 3 months ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆35Updated last year
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- Quite OK image compression Verilog implementation☆20Updated 4 months ago
- A bit-serial CPU☆18Updated 5 years ago
- Some materials and sample source for RV32 OS projects.☆22Updated 2 years ago
- GDB server to debug CPU simulation waveform traces☆44Updated 3 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago