Alternatives and similar repositories for Iron

Users that are interested in Iron are comparing it to the libraries listed below

• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 9 months ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated last year
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆42Updated 3 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 3 weeks ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆65Updated this week
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆76Updated last week
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated 3 months ago
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆111Updated last year
• eschkufz / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆23Updated 5 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆31Updated last year
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆36Updated 2 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 4 years ago
• Wren6991 / Hazard2
  Smol 2-stage RISC-V processor in nMigen
  ☆26Updated 4 years ago
• Mr-Bossman / KISC-V
  KISCV, a KISS principle riscv32i CPU
  ☆27Updated last year
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆39Updated last year
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆33Updated last year
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆98Updated last year
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆41Updated 3 years ago
• jevinskie / riscv-smol-linux-kernel
  Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM
  ☆24Updated 3 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆81Updated 2 weeks ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆61Updated 5 years ago
• tomverbeure / rt
  A Full Hardware Real-Time Ray-Tracer
  ☆111Updated 2 months ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆35Updated 2 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆49Updated last month
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆45Updated 8 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• meriac / OpenXC7-LiteX
  Container for compiling LiteX HDL FPGA designs using the free OpenXC7 tool chain and GitHub code spaces
  ☆26Updated 2 years ago
• kazkojima / colorlight-i5-tips
  Tiny tips for Colorlight i5 FPGA board
  ☆63Updated 4 years ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆68Updated 9 months ago