Alternatives and similar repositories for heterosim

Users that are interested in heterosim are comparing it to the libraries listed below

• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 3 weeks ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated last week
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• blucia0a / MultiCacheSim
  A Coherent Multiprocessor Cache Simulator Based on the SuperESCalar Cache Model
  ☆27Updated 11 years ago
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• fpgasystems / GPU-FPGA-Recommendation-System
  FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters
  ☆16Updated 4 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆40Updated 2 weeks ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated last year
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆31Updated 2 years ago
• lesc-ufv / cgra-routing
  SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.
  ☆11Updated 4 years ago
• riscvarchive / riscv-zfinx
  ☆12Updated last year
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 4 years ago
• pulp-platform / hero-sdk
  ⛔ DEPRECATED ⛔ HERO Software Development Kit
  ☆20Updated 3 years ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆33Updated 2 months ago
• CMU-SAFARI / NOCulator
  NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…
  ☆25Updated 2 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated 9 months ago
• ucb-bar / AuRORA
  Virtualized Accelerator Orchestration for Multi-Tenant Workloads
  ☆15Updated 6 months ago
• melver / mc2lib
  Memory consistency model checking and test generation library.
  ☆15Updated 8 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆22Updated 6 years ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆27Updated 2 weeks ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆26Updated 5 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• opencomputeproject / ODSA-BoW
  Repo for all activity related to the ODSA Bunch of Wires Specification
  ☆24Updated last year