HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design space exploration is enabled by a wide range of system configurations. A complete simulation flow with compiler support is provided so that a full system simulation can be performed with various performance me…
☆21Jul 11, 2016Updated 9 years ago
Alternatives and similar repositories for heterosim
Users that are interested in heterosim are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆44Sep 3, 2021Updated 4 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆17Sep 15, 2022Updated 3 years ago
- ReconOS - Operating System for Reconfigurable Hardware☆30Feb 4, 2022Updated 4 years ago
- Profile how CUDA applications create and modify data in memory.☆14Mar 22, 2018Updated 8 years ago
- ☆10Mar 3, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Memory consistency model checking and test generation library.☆15Oct 14, 2016Updated 9 years ago
- Update: we've moved our code to a new place! This fork is to maintain page references. New repo:☆10Aug 21, 2019Updated 6 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- ☆21Aug 23, 2021Updated 4 years ago
- ☆11Sep 25, 2021Updated 4 years ago
- Analyzer and simulator of logic circuit☆15May 8, 2017Updated 9 years ago
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Mar 13, 2025Updated last year
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Allows you to edit your apk file☆30Mar 28, 2012Updated 14 years ago
- Information on cores available on the Ulx3s ECP5 FPGA board☆14May 1, 2020Updated 6 years ago
- nMigen examples for the ULX3S board☆16Nov 30, 2020Updated 5 years ago
- Experiments for iCEstick evaluation board with iCE40HX-1k FPGA - using open source toolchain☆13Nov 24, 2015Updated 10 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- News and Paper Collections for Machine Learning Hardware☆22Apr 26, 2026Updated 2 months ago
- RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione☆30Mar 12, 2026Updated 3 months ago
- nMigen support for Xilinx Zynq devices☆17Nov 5, 2022Updated 3 years ago
- A bit-serial CPU☆20Sep 29, 2019Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Visual Analytics Tool for Dragonfly Network-based Supercomputers☆13Dec 8, 2016Updated 9 years ago
- ☆12Mar 14, 2023Updated 3 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- A Python-like programming language for testing and experimenting with concurrent programs.☆34Apr 7, 2026Updated 3 months ago
- MESIF cache coherency protocol for the GEM5 simulator☆15Jun 2, 2016Updated 10 years ago
- Experiments with Yosys cxxrtl backend☆50Jan 16, 2025Updated last year
- A Verilog parser for Haskell.☆37Jul 6, 2021Updated 5 years ago
- Artifact, reproducibility, and testing utilites for gem5☆23Jul 1, 2021Updated 5 years ago
- Build LLVM Toolchain targeting a custom sysroot - Clang, LLD, Binutils (gold), compiler-rt, libc++, libcxxabi, libunwind☆14May 21, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An implementation of memcpy for amd64 with clang/gcc☆15Feb 7, 2022Updated 4 years ago
- Using e-graphs for logic synthesis (ICCAD'25)☆35Jun 11, 2026Updated 3 weeks ago
- A enumerator for MLIR, relying on the information given by IRDL.☆26Jun 23, 2026Updated 2 weeks ago
- Graph accelerator on FPGAs and ASICs☆11Aug 16, 2018Updated 7 years ago
- ☆10Jun 28, 2019Updated 7 years ago
- C++ HDL (Hardware Description Language)☆48Updated this week
- Analog Circuit Simulator☆26Sep 6, 2024Updated last year