YosysHQ / prjpeppercornLinks
Project Peppercorn - GateMate FPGA Bitstream Documentation
☆30Updated this week
Alternatives and similar repositories for prjpeppercorn
Users that are interested in prjpeppercorn are comparing it to the libraries listed below
Sorting:
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated last month
- Use ECP5 JTAG port to interact with user design☆32Updated 4 years ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆52Updated this week
- A configurable USB 2.0 device core☆32Updated 5 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- KiCad symbol library for sky130 and gf180mcu PDKs☆32Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆27Updated 2 months ago
- assorted library of utility cores for amaranth HDL☆97Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated last year
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our …☆33Updated 10 months ago
- Development board for GateMateA1 CCGM1A1 FPGA from Cologne Chip with PS2 VGA 64Mbit RAM RP2040☆35Updated 2 weeks ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆81Updated 2 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆91Updated 6 months ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32Updated 2 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Updated 2 years ago
- ☆71Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated last week
- DVI video out example for prjtrellis☆17Updated 6 years ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Updated last year
- Simplified environment for litex☆14Updated 5 years ago
- Experimental flows using nextpnr for Xilinx devices☆54Updated last month
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- The open-source Zynq 7000 BSP generator for openXC7☆48Updated 11 months ago
- LiteX development baseboards arround the SQRL Acorn.☆72Updated 9 months ago
- Nitro USB FPGA core☆85Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated last week