Alternatives and similar repositories for prjpeppercorn:

Users that are interested in prjpeppercorn are comparing it to the libraries listed below

• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆21Updated last year
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆26Updated 3 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• Blinkinlabs / QL-EOS-S3-breakout
  ☆12Updated 3 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆24Updated last month
• lambdaconcept / amaranth-to-litex
  Use amaranth-to-litex to simply import Amaranth code into a Litex project.
  ☆12Updated 11 months ago
• no2fpga / no2muacm
  Drop In USB CDC ACM core for iCE40 FPGA
  ☆34Updated 3 years ago
• hansfbaier / colorlight-qmtech-adapter
  Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor
  ☆18Updated 2 years ago
• ECP5-PCIe / ECP5-Utils
  Utilities for the ECP5 FPGA
  ☆18Updated 3 years ago
• tmeissner / gatemate_experiments
  Experiments with Cologne Chip's GateMate FPGA architecture
  ☆15Updated last year
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 4 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆30Updated 4 years ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆36Updated 3 months ago
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆15Updated last year
• tomverbeure / fpga_quick_ram_update
  Quickly update a bitstream with new RAM contents
  ☆15Updated 3 years ago
• kazkojima / lunauac2-pdm
  A LiteX module implementing a USB UAC2 module with simple PDM in/out
  ☆14Updated 3 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 5 months ago
• blackmesalabs / sump3
  sump3 logic analyzer
  ☆19Updated 3 months ago
• ydnatag / nmigen-cocotb
  cocotb extension for nMigen
  ☆16Updated 3 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆86Updated 6 months ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆12Updated 6 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• tongchen126 / fpga_pcie_ethernet
  ☆15Updated 2 years ago
• regymm / GenZ
  The open-source Zynq 7000 BSP generator for openXC7
  ☆24Updated 2 months ago
• micro-FPGA / CRUVI
  CRUVI Standard Specifications
  ☆18Updated 10 months ago
• lethalbit / kicad-pdk-libs
  KiCad symbol library for sky130 and gf180mcu PDKs
  ☆32Updated last year
• 360nosc0pe / scope
  Siglent SDS1x0xX-E FPGA bitstreams
  ☆41Updated 3 months ago
• daveshah1 / prjtrellis-dvi
  DVI video out example for prjtrellis
  ☆16Updated 6 years ago