YosysHQ / prjpeppercornLinks
Project Peppercorn - GateMate FPGA Bitstream Documentation
☆23Updated 2 weeks ago
Alternatives and similar repositories for prjpeppercorn
Users that are interested in prjpeppercorn are comparing it to the libraries listed below
Sorting:
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆13Updated this week
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 5 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated last week
- Use ECP5 JTAG port to interact with user design☆31Updated 4 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Simplified environment for litex☆14Updated 4 years ago
- USB virtual model in C++ for Verilog☆31Updated 9 months ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆15Updated last year
- ☆12Updated 4 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆19Updated 3 years ago
- Development board for GateMateA1 CCGM1A1 FPGA from Cologne Chip with PS2 VGA 64Mbit RAM RP2040☆30Updated 7 months ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Updated last year
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- assorted library of utility cores for amaranth HDL☆94Updated 10 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆52Updated 2 months ago
- a USB2 highspeed device core, written in amaranth HDL☆49Updated 10 months ago
- DVI video out example for prjtrellis☆16Updated 6 years ago
- USB Full-Speed core written in migen/LiteX☆12Updated 5 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated 7 months ago
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 4 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 3 years ago
- USB DFU bootloader gateware / firmware for FPGAs☆67Updated 9 months ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Updated 3 years ago
- ☆20Updated 3 years ago
- My pergola FPGA projects☆30Updated 4 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago