YosysHQ / prjpeppercornLinks
Project Peppercorn - GateMate FPGA Bitstream Documentation
☆21Updated this week
Alternatives and similar repositories for prjpeppercorn
Users that are interested in prjpeppercorn are comparing it to the libraries listed below
Sorting:
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆11Updated 2 weeks ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated 3 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated this week
- Experiments with Cologne Chip's GateMate FPGA architecture☆15Updated last year
- Use ECP5 JTAG port to interact with user design☆28Updated 3 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Simplified environment for litex☆14Updated 4 years ago
- ☆12Updated 3 years ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆38Updated 5 months ago
- USB virtual model in C++ for Verilog☆30Updated 7 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆30Updated 2 years ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆19Updated 2 years ago
- A configurable USB 2.0 device core☆31Updated 4 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 3 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆15Updated 3 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- nMigen examples for the ULX3S board☆16Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆12Updated 2 years ago
- DDR3 controller for nMigen (WIP)☆14Updated last year
- I want to learn [n]Migen.☆41Updated 5 years ago
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆11Updated this week
- ☆45Updated 2 years ago
- Development board for GateMateA1 CCGM1A1 FPGA from Cologne Chip with PS2 VGA 64Mbit RAM RP2040☆29Updated 5 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- ☆20Updated 2 years ago