jevinskie / General-Slow-DDR3-Interface
A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
☆12Updated 2 years ago
Alternatives and similar repositories for General-Slow-DDR3-Interface:
Users that are interested in General-Slow-DDR3-Interface are comparing it to the libraries listed below
- Quickly update a bitstream with new RAM contents☆15Updated 3 years ago
- PLEASE MOVE TO PAWSv2☆17Updated 2 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆16Updated 3 years ago
- Mini CPU design with JTAG UART support☆19Updated 3 years ago
- Use ECP5 JTAG port to interact with user design☆26Updated 3 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆40Updated 4 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 6 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆21Updated 3 months ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆35Updated last year
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- PS2 interface☆17Updated 7 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆37Updated 2 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆15Updated last year
- Test of a RP2040 PMOD attached to a LiteX SoC.☆25Updated last year
- QQSPI Pmod-compatible 32MB PSRAM module☆15Updated last year
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆17Updated 2 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆33Updated 3 years ago
- Misc iCE40 specific cores☆14Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- An FPGA/PCI Device Reference Platform☆28Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆37Updated 8 months ago
- A complete HDMI transmitter implementation in VHDL☆21Updated 2 weeks ago
- Smol 2-stage RISC-V processor in nMigen☆26Updated 3 years ago
- SDRAM controller with multiple wishbone slave ports☆28Updated 6 years ago
- Documentation and tools related to DECA FPGA board☆21Updated last year
- XC2064 bitstream documentation☆16Updated 6 years ago
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year
- Master-thesis-final☆18Updated last year