calyxir / calyx-riscv
RISCV Core written in Calyx
☆16Updated 8 months ago
Alternatives and similar repositories for calyx-riscv:
Users that are interested in calyx-riscv are comparing it to the libraries listed below
- Verilog AST☆21Updated last year
- ☆40Updated 3 years ago
- CHERI-RISC-V model written in Sail☆58Updated 2 weeks ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- Verilator Porcelain☆48Updated last year
- Reticle evaluation (PLDI 2021)☆12Updated 4 years ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆13Updated 5 months ago
- 21st century electronic design automation tools, written in Rust.☆30Updated this week
- A Hardware Pipeline Description Language☆44Updated last year
- BTOR2 MLIR project☆25Updated last year
- an experiment to run plugin in firtool pipeline☆9Updated last year
- Easy SMT solver interaction☆35Updated last month
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆20Updated 3 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆59Updated this week
- 🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆42Updated 3 weeks ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated last month
- Logic circuit analysis and optimization☆35Updated 6 months ago
- A Just-In-Time Compiler for Verilog from VMware Research☆22Updated 4 years ago
- A core language for rule-based hardware design 🦑☆148Updated 6 months ago
- The LLHD reference simulator.☆37Updated 4 years ago
- FPGA synthesis tool powered by program synthesis☆41Updated last week
- The source code to the Voss II Hardware Verification Suite☆56Updated this week
- Testing processors with Random Instruction Generation☆37Updated 3 weeks ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- Manythread RISC-V overlay for FPGA clusters☆36Updated 2 years ago
- A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one☆69Updated this week
- Whisk: 16-bit serial processor for TT02☆13Updated 6 months ago
- ☆19Updated this week
- Native Rust implementation of the FST waveform format from GTKWave.☆12Updated last month
- ☆25Updated 2 years ago