calyxir / calyx-riscvLinks
RISCV Core written in Calyx
☆17Updated last year
Alternatives and similar repositories for calyx-riscv
Users that are interested in calyx-riscv are comparing it to the libraries listed below
Sorting:
- Verilog AST☆21Updated 2 years ago
- Verilator Porcelain☆49Updated 2 years ago
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆74Updated last month
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Updated last year
- Logic circuit analysis and optimization☆42Updated 3 months ago
- A Hardware Pipeline Description Language☆49Updated 4 months ago
- ☆40Updated 4 years ago
- 21st century electronic design automation tools, written in Rust.☆33Updated last week
- Time-sensitive affine types for predictable hardware generation☆146Updated 3 weeks ago
- CHERI-RISC-V model written in Sail☆66Updated 4 months ago
- A core language for rule-based hardware design 🦑☆165Updated last month
- BTOR2 MLIR project☆26Updated last year
- ☆36Updated 2 months ago
- Fearless hardware design☆183Updated 3 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆102Updated this week
- Interpreter and compiler for the ISA specification language "Architecture Specification Language" (ASL)☆24Updated 2 months ago
- The source code to the Voss II Hardware Verification Suite☆56Updated this week
- The LLHD reference simulator.☆39Updated 5 years ago
- work in progress, playing around with btor2 in rust☆12Updated last week
- A hardware compiler based on LLHD and CIRCT☆264Updated 5 months ago
- FPGA synthesis tool powered by program synthesis☆52Updated last month
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated last month
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆96Updated 2 months ago
- Testing processors with Random Instruction Generation☆50Updated last week
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spad…☆34Updated this week
- ☆15Updated last week
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 5 months ago
- End-to-end synthesis and P&R toolchain☆92Updated 2 months ago
- Reticle evaluation (PLDI 2021)☆12Updated 4 years ago