Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
☆189Mar 10, 2024Updated 2 years ago
Alternatives and similar repositories for usb_cdc
Users that are interested in usb_cdc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Full Speed USB DFU interface for FPGA and ASIC designs☆20Mar 10, 2024Updated 2 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- A compact USB HID host FPGA core supporting keyboards, mice and gamepads.☆162Mar 22, 2025Updated last year
- An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA comm…☆879Dec 6, 2024Updated last year
- Basic USB-CDC device core (Verilog)☆89May 15, 2021Updated 4 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A huge VHDL library for FPGA and digital ASIC development☆456Apr 24, 2026Updated last week
- USB Serial on the TinyFPGA BX☆142Jun 20, 2021Updated 4 years ago
- RISC-V Playground on Nandland Go☆16Mar 2, 2023Updated 3 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Sep 5, 2021Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆99Jun 6, 2020Updated 5 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Programmable multichannel ADPCM decoder for FPGA☆26Dec 28, 2020Updated 5 years ago
- USB serial device (CDC-ACM)☆45Jun 28, 2020Updated 5 years ago
- An attempt to recreate the RP2040 PIO in an FPGA☆315Jun 6, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Opensource DDR3 Controller☆428Jan 18, 2026Updated 3 months ago
- Soft USB for LiteX☆51Oct 6, 2025Updated 6 months ago
- Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.☆167Jun 24, 2021Updated 4 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Apr 22, 2024Updated 2 years ago
- Universal utility for programming FPGA☆1,615Updated this week
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆107Aug 28, 2025Updated 8 months ago
- ☆17Apr 7, 2022Updated 4 years ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆113Jul 20, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Mini CPU design with JTAG UART support☆21Jun 8, 2021Updated 4 years ago
- WCH CH569 SerDes Reverse Engineering☆30Aug 13, 2022Updated 3 years ago
- Use an MPSSE FTDI device as a JTAG interface in Quartus tools☆29Feb 22, 2024Updated 2 years ago
- Nitro USB FPGA core☆87Mar 1, 2026Updated 2 months ago
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆225Feb 19, 2026Updated 2 months ago
- a USB2 highspeed device core, written in amaranth HDL☆53Sep 17, 2024Updated last year
- A full-speed device-side USB peripheral core written in Verilog.☆238Oct 30, 2022Updated 3 years ago
- KISCV, a KISS principle riscv32i CPU☆28Jan 11, 2025Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆61Nov 14, 2025Updated 5 months ago
- An open source USB bootloader for FPGAs☆398Sep 15, 2023Updated 2 years ago
- 3-stage RV32IMACZb* processor with debug☆1,042Apr 23, 2026Updated last week
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,412Apr 13, 2026Updated 2 weeks ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆589Oct 10, 2021Updated 4 years ago