ulixxe / usb_cdcLinks
Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
☆172Updated last year
Alternatives and similar repositories for usb_cdc
Users that are interested in usb_cdc are comparing it to the libraries listed below
Sorting:
- ☆110Updated 2 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 5 years ago
- USB3 PIPE interface for Xilinx 7-Series☆216Updated 3 years ago
- CoreScore☆156Updated 4 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆90Updated 5 years ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆79Updated last week
- Basic USB-CDC device core (Verilog)☆79Updated 4 years ago
- Board definitions for Amaranth HDL☆117Updated 2 months ago
- A full-speed device-side USB peripheral core written in Verilog.☆232Updated 2 years ago
- Naive Educational RISC V processor☆84Updated 2 weeks ago
- A wishbone controlled scope for FPGA's☆82Updated last year
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆105Updated 11 months ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆272Updated last year
- Minimal DVI / HDMI Framebuffer☆81Updated 4 years ago
- FuseSoC standard core library☆143Updated 3 weeks ago
- USB Serial on the TinyFPGA BX☆136Updated 4 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆294Updated last month
- Experimental flows using nextpnr for Xilinx devices☆240Updated 8 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆79Updated last year
- VHDL library 4 FPGAs☆179Updated this week
- Verilog wishbone components☆115Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆94Updated last week
- Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs☆111Updated 3 years ago
- ☆79Updated last year
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆43Updated 3 years ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- Example LED blinking project for your FPGA dev board of choice☆177Updated 3 weeks ago
- A compact USB HID host FPGA core supporting keyboards, mice and gamepads.☆127Updated 3 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago