ben-marshall / croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
☆43Updated 2 years ago
Related projects: ⓘ
- General Purpose AXI Direct Memory Access☆44Updated 4 months ago
- DUTH RISC-V Superscalar Microprocessor☆29Updated 4 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆48Updated 3 weeks ago
- Platform Level Interrupt Controller☆34Updated 4 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated 7 months ago
- IEEE 754 floating point library in system-verilog and vhdl☆53Updated 3 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆29Updated 3 years ago
- RISCV model for Verilator/FPGA targets☆44Updated 4 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆20Updated 6 years ago
- DUTH RISC-V Microprocessor☆18Updated 3 years ago
- ☆35Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆39Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆28Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆57Updated 5 months ago
- The memory model was leveraged from micron.☆18Updated 6 years ago
- ☆34Updated 7 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆26Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆26Updated last year
- ☆44Updated 3 years ago
- ☆23Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆43Updated 3 months ago
- Xilinx AXI VIP example of use☆29Updated 3 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆25Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆16Updated 5 months ago
- ☆68Updated 11 months ago
- A Fast, Low-Overhead On-chip Network☆115Updated this week
- APB UVC ported to Verilator☆11Updated 10 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆56Updated 3 years ago
- A simple DDR3 memory controller☆49Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆38Updated 3 months ago