ben-marshall / croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
☆44Updated 3 years ago
Alternatives and similar repositories for croyde-riscv:
Users that are interested in croyde-riscv are comparing it to the libraries listed below
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- ☆27Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Contains commonly used UVM components (agents, environments and tests).☆29Updated 6 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated 11 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆27Updated 7 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆29Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last month
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 6 months ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- ☆27Updated 3 weeks ago
- ☆55Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆29Updated 4 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆24Updated 6 years ago
- ☆20Updated 5 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- Generate UVM testbench framework template files with Python 3☆25Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆59Updated 4 years ago