A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
☆48Jan 31, 2022Updated 4 years ago
Alternatives and similar repositories for croyde-riscv
Users that are interested in croyde-riscv are comparing it to the libraries listed below
Sorting:
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- ☆19Aug 27, 2022Updated 3 years ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆596Jan 3, 2026Updated 2 months ago
- an open source uvm verification platform for e200 (riscv)☆29May 5, 2018Updated 7 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- RISC-V Rocket on the Digilent Zybo Board☆21Aug 6, 2014Updated 11 years ago
- ☆25Aug 9, 2022Updated 3 years ago
- XCrypto: a cryptographic ISE for RISC-V☆92Jan 5, 2023Updated 3 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆27Jan 21, 2026Updated last month
- RISC-V Matrix Specification☆23Dec 2, 2024Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Feb 3, 2026Updated last month
- RISC-V Nox core☆71Jul 22, 2025Updated 7 months ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆107Nov 14, 2018Updated 7 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- Python bindings for coreir☆11Sep 13, 2023Updated 2 years ago
- Atom Hardware IDE☆13May 4, 2021Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture