ben-marshall / croyde-riscvLinks
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
☆47Updated 3 years ago
Alternatives and similar repositories for croyde-riscv
Users that are interested in croyde-riscv are comparing it to the libraries listed below
Sorting:
- ☆30Updated last month
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- Platform Level Interrupt Controller☆43Updated last year
- RISC-V Nox core☆68Updated 3 months ago
- General Purpose AXI Direct Memory Access☆60Updated last year
- 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated 2 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- ☆99Updated 2 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆31Updated 3 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 9 years ago
- Clarvi simple RISC-V processor for teaching☆58Updated 8 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 8 months ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- BlackParrot on Zynq☆48Updated this week
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- DUTH RISC-V Microprocessor☆22Updated 10 months ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆17Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- ☆67Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago