ben-marshall / croyde-riscvLinks
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
☆48Updated 3 years ago
Alternatives and similar repositories for croyde-riscv
Users that are interested in croyde-riscv are comparing it to the libraries listed below
Sorting:
- ☆33Updated last month
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- Platform Level Interrupt Controller☆43Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 3 weeks ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- RISC-V Nox core☆71Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- DUTH RISC-V Microprocessor☆23Updated last year
- General Purpose AXI Direct Memory Access☆62Updated last year
- BlackParrot on Zynq☆47Updated last week
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated 2 weeks ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- Simple single-port AXI memory interface☆48Updated last year
- ☆31Updated 5 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- ☆110Updated last month
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆32Updated 2 weeks ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year