Mr-Bossman / KISC-VLinks
KISCV, a KISS principle riscv32i CPU
☆25Updated 8 months ago
Alternatives and similar repositories for KISC-V
Users that are interested in KISC-V are comparing it to the libraries listed below
Sorting:
- ☆17Updated 4 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated 3 weeks ago
- Iron: selectively turn RISC-V binaries into hardware☆23Updated 2 years ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 2 weeks ago
- FLIX-V: FPGA, Linux and RISC-V☆42Updated last year
- Reusable Verilog 2005 components for FPGA designs☆46Updated 7 months ago
- A pipelined RISC-V processor☆58Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- ☆15Updated 4 months ago
- Doom classic port to lightweight RISC‑V☆95Updated 3 years ago
- Exploring gate level simulation☆58Updated 5 months ago
- PicoRV☆44Updated 5 years ago
- A design for TinyTapeout☆17Updated 3 years ago
- Virtual Development Board☆61Updated 3 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆89Updated 3 months ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆55Updated 5 months ago
- Quite OK image compression Verilog implementation☆22Updated 9 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 3 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆56Updated 2 weeks ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆16Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- ☆61Updated 4 years ago
- RISC-V 32-bit Linux From Scratch☆35Updated 5 years ago
- Soft USB for LiteX☆50Updated 2 years ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆109Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆50Updated last year
- Generate Zynq configurations without using the vendor GUI☆30Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year