MichaelBell / nanoVLinks
RISC-V RV32E core designed for minimal area
☆16Updated 6 months ago
Alternatives and similar repositories for nanoV
Users that are interested in nanoV are comparing it to the libraries listed below
Sorting:
- A Risc-V SoC for Tiny Tapeout☆18Updated 2 months ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 3 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆60Updated 3 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆15Updated last week
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆27Updated 5 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆15Updated last year
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- Use ECP5 JTAG port to interact with user design☆28Updated 3 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆57Updated this week
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Wishbone interconnect utilities☆41Updated 3 months ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆29Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 5 months ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆30Updated 2 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 3 weeks ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆12Updated 3 months ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆26Updated 3 months ago
- A SoC for DOOM☆17Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆93Updated 9 months ago
- QQSPI Pmod-compatible 32MB PSRAM module☆15Updated last year
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated this week
- LunaPnR is a place and router for integrated circuits☆46Updated 6 months ago
- simple wishbone client to read buttons and write leds☆18Updated last year
- PLEASE MOVE TO PAWSv2☆17Updated 3 years ago