MichaelBell / nanoVLinks
RISC-V RV32E core designed for minimal area
☆23Updated last year
Alternatives and similar repositories for nanoV
Users that are interested in nanoV are comparing it to the libraries listed below
Sorting:
- A Risc-V SoC for Tiny Tapeout☆43Updated 3 weeks ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆66Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated 2 weeks ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆34Updated 10 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆23Updated 2 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆44Updated 4 years ago
- RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K☆41Updated last year
- Basic Pong you can extend with rotary, sound, vga generator and autopilot☆11Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32Updated 2 years ago
- A SoC for DOOM☆20Updated 4 years ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆104Updated 4 months ago
- ☆37Updated last year
- simple wishbone client to read buttons and write leds☆19Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated last month
- Re-coded Gowin GW1N primitives for Verilator use☆20Updated 3 years ago
- RISC-V Playground on Nandland Go☆16Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated last week
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆103Updated 2 years ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆33Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆92Updated 7 years ago
- An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA☆87Updated 3 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆27Updated 2 months ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Updated 2 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70Updated 3 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Updated 2 years ago
- ☆15Updated 7 months ago
- ☆71Updated last year
- Master-thesis-final☆19Updated 2 years ago