Alternatives and similar repositories for waveform-generator

Users that are interested in waveform-generator are comparing it to the libraries listed below

• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 4 years ago
• tomverbeure / intel_jtag_primitive_blog
  How to use the Intel JTAG primitive without using virtual JTAG
  ☆17Updated 4 years ago
• himanshu5-prog / vortexGPU
  ☆24Updated 4 years ago
• tongchen126 / fpga_pcie_ethernet
  ☆16Updated 3 years ago
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 5 years ago
• BLangOS / VexRiscV_with_HW-GDB_Server
  VexRiscV system with GDB-Server in Hardware
  ☆21Updated 2 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆19Updated 3 years ago
• azonenberg / jtaghal
  JTAG Hardware Abstraction Library
  ☆37Updated 2 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 4 years ago
• steveicarus / simbus
  Icarus SIMBUS
  ☆20Updated 6 years ago
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆20Updated last year
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆66Updated 2 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 2 months ago
• enjoy-digital / pcie_analyzer
  PCIe analyzer experiments
  ☆63Updated 5 years ago
• merlinepedra25 / Xilinx-Unprotect
  ☆53Updated 3 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆59Updated 8 months ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆30Updated last year
• jevinskie / liteluna
  LiteX LUNA USB stack integration
  ☆14Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆32Updated last year
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆14Updated 3 months ago
• fallen / SucreLA
  Open source Logic Analyzer based on LiteX SoC
  ☆26Updated 8 months ago
• FPGA-Research / FPGAVirusScanner
  Program to scan for malicious FPGA designs.
  ☆17Updated 4 years ago
• ChrisPVille / jtaglet
  Easy-to-use JTAG TAP and Debug Controller core written in Verilog
  ☆34Updated 7 years ago
• tomverbeure / usb_system
  SpinalHDL USB system for the ULPI based Arrow DECA board
  ☆20Updated 3 years ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆39Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆53Updated 2 years ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆63Updated 2 weeks ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• mattvenn / understanding-tinyfpga-bootloader
  understanding the tinyfpga bootloader
  ☆25Updated 7 years ago
• whitequark / Yumewatari
  妖刀夢渡
  ☆63Updated 6 years ago