Alternatives and similar repositories for waveform-generator

Users that are interested in waveform-generator are comparing it to the libraries listed below

• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 4 years ago
• himanshu5-prog / vortexGPU
  ☆24Updated 4 years ago
• tongchen126 / fpga_pcie_ethernet
  ☆17Updated 3 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆20Updated 3 years ago
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆20Updated last year
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 4 years ago
• tomverbeure / intel_jtag_primitive_blog
  How to use the Intel JTAG primitive without using virtual JTAG
  ☆17Updated 4 years ago
• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆17Updated 3 years ago
• BLangOS / VexRiscV_with_HW-GDB_Server
  VexRiscV system with GDB-Server in Hardware
  ☆21Updated 2 years ago
• azonenberg / jtaghal
  JTAG Hardware Abstraction Library
  ☆37Updated 2 years ago
• defparam / PCI2Nano-PCB
  An FPGA/PCI Device Reference Platform
  ☆32Updated 5 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 3 weeks ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆31Updated last week
• m-labs / nmigen-boards
  Board and connector definition files for nMigen
  ☆30Updated 5 years ago
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 5 years ago
• jevinskie / liteluna
  LiteX LUNA USB stack integration
  ☆14Updated 3 years ago
• steveicarus / simbus
  Icarus SIMBUS
  ☆20Updated 6 years ago
• FPGA-Research / FPGAVirusScanner
  Program to scan for malicious FPGA designs.
  ☆17Updated 4 years ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆65Updated this week
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 9 months ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated 4 months ago
• wyvernSemi / usbModel
  USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL
  ☆32Updated last year
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 4 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated 2 months ago
• merlinepedra25 / Xilinx-Unprotect
  ☆54Updated 3 years ago
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆14Updated 4 months ago
• gojimmypi / VerilogLanguageExtension
  Verilog Language Extension for Visual Studio
  ☆20Updated 3 weeks ago
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 5 years ago
• enjoy-digital / pcie_analyzer
  PCIe analyzer experiments
  ☆64Updated 5 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆31Updated 4 months ago