[Moved to Codeberg] Another size-optimized RISC-V CPU for your consideration.
☆61May 10, 2026Updated last month
Alternatives and similar repositories for sentinel
Users that are interested in sentinel are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- KISCV, a KISS principle riscv32i CPU☆28Jan 11, 2025Updated last year
- RISC-V Processor written in Amaranth HDL☆39Jan 21, 2022Updated 4 years ago
- Small 32-bit RISC-V CPU with a half-width datapath inspired by the 68000☆16Dec 21, 2023Updated 2 years ago
- Hot Reconfiguration Technology demo☆42Aug 23, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Smol 2-stage RISC-V processor in nMigen☆26May 6, 2021Updated 5 years ago
- ☆23Jul 29, 2025Updated 10 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆116Jul 20, 2024Updated last year
- ☆49Feb 26, 2023Updated 3 years ago
- Awesome projects using the Amaranth HDL☆20Feb 6, 2025Updated last year
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆34Aug 27, 2024Updated last year
- A configurable USB 2.0 device core☆32Jun 12, 2020Updated 6 years ago
- DVI video out example for prjtrellis☆17Jan 20, 2019Updated 7 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆33Oct 15, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- System on Chip toolkit for Amaranth HDL☆101May 23, 2026Updated 3 weeks ago
- buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"☆26Apr 23, 2024Updated 2 years ago
- 16 bit RISC-V proof of concept☆26Jan 5, 2026Updated 5 months ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆37Jul 2, 2023Updated 2 years ago
- VexRiscV system with GDB-Server in Hardware☆21Jul 5, 2023Updated 2 years ago
- A RISC-V CPU implementation☆17Apr 9, 2020Updated 6 years ago
- OpenGL 1.x implementation for FPGAs☆134May 28, 2026Updated 2 weeks ago
- A Rust embedded HAL crate for LiteX cores☆31Jun 1, 2026Updated last week
- RISC-V RV32E core designed for minimal area☆27Nov 17, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆14Jan 15, 2024Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆50Jan 16, 2025Updated last year
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Apr 22, 2024Updated 2 years ago
- Baremetal Backtracing on RISC-V☆16Jun 22, 2021Updated 4 years ago
- Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs☆34Jul 15, 2021Updated 4 years ago
- Basic Pong you can extend with rotary, sound, vga generator and autopilot☆11Oct 26, 2021Updated 4 years ago
- Fault Injection Automatic Test Equipment☆15Nov 22, 2021Updated 4 years ago
- ECP5 FPGA in an "S7 Mini" form factor☆90Aug 13, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A 32-bit RISC-V soft processor☆328Jan 26, 2026Updated 4 months ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆30Jul 10, 2024Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆100Jun 6, 2020Updated 6 years ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- I want to learn [n]Migen.☆44Jan 26, 2020Updated 6 years ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆94Mar 12, 2026Updated 3 months ago