zslwyuan / AutoCellLibXLinks
AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
☆15Updated 2 years ago
Alternatives and similar repositories for AutoCellLibX
Users that are interested in AutoCellLibX are comparing it to the libraries listed below
Sorting:
- Collection of digital hardware modules & projects (benchmarks)☆59Updated 3 weeks ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆48Updated last week
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆26Updated last month
- ☆22Updated 11 months ago
- The first version of TritonPart☆26Updated last year
- Research paper based on or related to ABC.☆43Updated last week
- ☆17Updated 2 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆48Updated 4 months ago
- GPU-based logic synthesis tool☆81Updated 10 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆30Updated 7 months ago
- ☆31Updated 3 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆104Updated last year
- A parallel global router using the Galois framework☆29Updated last year
- This is a python repo for flattening Verilog☆16Updated 3 weeks ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆18Updated last month
- ☆24Updated last year
- ☆23Updated 6 months ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 5 months ago
- ☆28Updated last year
- ☆24Updated 4 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆25Updated 2 weeks ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 4 months ago
- EDA physical synthesis optimization kit☆57Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated last month
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated 8 months ago
- DATC RDF☆50Updated 4 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆27Updated last week
- ☆16Updated 4 years ago