zslwyuan / AutoCellLibXLinks
AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
☆18Updated 3 years ago
Alternatives and similar repositories for AutoCellLibX
Users that are interested in AutoCellLibX are comparing it to the libraries listed below
Sorting:
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago
- GPU-based logic synthesis tool☆93Updated this week
- Collection of digital hardware modules & projects (benchmarks)☆69Updated last week
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆35Updated 4 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆107Updated last year
- ☆25Updated last year
- ☆26Updated 4 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆86Updated 6 months ago
- ☆27Updated last year
- ☆76Updated 5 months ago
- Research paper based on or related to ABC.☆59Updated last week
- The first version of TritonPart☆29Updated last year
- ☆31Updated 3 years ago
- ☆18Updated 4 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆58Updated 10 months ago
- ☆20Updated 3 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆40Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆54Updated 10 months ago
- ☆89Updated 4 months ago
- Logic optimization and technology mapping tool.☆19Updated 2 years ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆66Updated 5 months ago
- ☆41Updated last year
- This is a python repo for flattening Verilog☆20Updated 6 months ago
- ☆55Updated 5 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- DATC RDF☆50Updated 5 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆34Updated 5 months ago
- ☆40Updated 2 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 4 years ago
- ☆31Updated 2 years ago